Thin film transistor

ABSTRACT

A thin film transistor is provided, which includes a gate electrode layer over a substrate, a gate insulating layer over the gate electrode layer, a layer including an amorphous semiconductor over the gate insulating layer, a pair of crystal regions over the layer including the amorphous semiconductor, and source and drain regions over and in contact with the pair of crystal regions. The source and drain regions include a microcrystalline semiconductor layer to which an impurity imparting one conductivity type is added.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a thin film transistor and a method formanufacturing the thin film transistor, and a semiconductor device and adisplay device using the thin film transistor.

2. Description of the Related Art

As a kind of field-effect transistor, a thin film transistor in which achannel formation region is formed in a semiconductor layer formed overa substrate having an insulating surface is known. Techniques in whichamorphous silicon, microcrystalline silicon, or polycrystalline siliconis used for the semiconductor layer used in the thin film transistorhave been disclosed.

Further, a technique for increasing the amount of current flowingbetween a source and a drain by forming contact layers in contact with asource electrode layer and a drain electrode layer (also referred to asa source region and a drain region) of a thin film transistor with theuse of an n-type microcrystalline silicon has been disclosed (see PatentDocument 1).

On the other hand, the size of a transistor has been reduced in order toimprove resolution of a display device and increase the aperture ratioin a pixel, and a thin film transistor with a short channel length whichis approximately an exposure limit of a light-exposure apparatus (MPA)has been considered. In a thin film transistor with a short channellength, an on current can be increased and a threshold voltage can bereduced.

-   [Patent Document 1] Japanese Published Patent Application No.    H3-185840

SUMMARY OF THE INVENTION

In the case of a conventional microcrystalline semiconductor layer, anamorphous semiconductor layer having poor crystallinity and a lot ofdefects is deposited due to lattice mismatch with a base film in anearly stage of deposition. Therefore, even when an n-typemicrocrystalline silicon film is formed as a contact layer, a lowdensity layer having low density and a lot of defects is formed at theinterface between the base film and the contact layer, which causes aproblem that a barrier is formed at the interface between the base filmand the contact layer, resistance between a source region and a drainregion is increased, and thus the amount of current flowing through theregions is reduced.

Further, in general, in the case where a plasma CVD apparatus has lowpower in the deposition conditions of the n-type microcrystallinesilicon film, formation of an amorphous layer in an early stage ofdeposition of the n-type microcrystalline silicon film can besuppressed. However, high power is required for crystallization fordepositing the n-type microcrystalline silicon film. That is, the levelof power for forming the n-type microcrystalline silicon film and thelevel of power for suppressing formation of the low density layer in anearly stage of deposition of the n-type microcrystalline silicon filmare contradictory to each other, which makes it difficult to form themicrocrystalline silicon film in which the proportion of the low densitylayer at the interface is reduced.

On the other hand, FIGS. 21A to 21D illustrate structures ofinverted-staggered thin film transistors. FIG. 21A is a cross-sectionalview of a thin film transistor with a long channel length which is about100 μm, in which a gate electrode layer 903 is formed over a substrate901, a gate insulating layer 905 is formed over the gate electrode layer903, a semiconductor layer 907 including a channel formation region isformed over the gate insulating layer 905, and a source region 909 s anda drain region 909 d which are paired are formed over the semiconductorlayer 907. Further, a source electrode layer 911 s and a drain electrodelayer 911 d are formed over the source region 909 s and the drain region909 d, respectively. Further, the channel length of the thin filmtransistor illustrated in FIG. 21A is denoted by L1.

FIG. 21B illustrates an equivalent circuit of the thin film transistorillustrated in FIG. 21A. The resistance between the source region 909 sand the semiconductor layer 907, the resistance of the channel formationregion of the semiconductor layer 907, and the resistance between thesemiconductor layer 907 and the drain region 909 d are denoted by Rs,Rch1, and Rd, respectively.

FIG. 21C is a cross-sectional view of a thin film transistor with ashort channel length which is 10 μm or less, preferably 5 μm or less, inwhich the gate electrode layer 903 is formed over the substrate 901, thegate insulating layer 905 is formed over the gate electrode layer 903, asemiconductor layer 913 including a channel formation region is formedover the gate insulating layer 905, and the source region 909 s and thedrain region 909 d which are paired are formed over the semiconductorlayer 913. Further, the source electrode layer 911 s and the drainelectrode layer 911 d are formed over the source region 909 s and thedrain region 909 d, respectively. Further, the channel length of thethin film transistor illustrated in FIG. 21C is denoted by L2 (0<L2<L1).

FIG. 21D illustrates an equivalent circuit of the thin film transistorillustrated in FIG. 21C. The resistance between the source region 909 sand the semiconductor layer 913, the resistance of the channel formationregion of the semiconductor layer 913, and the resistance between thesemiconductor layer 913 and the drain region 909 d are denoted by Rs,Rch2, and Rd, respectively.

In the thin film transistor with a long channel length which is about100 μn in FIGS. 21A and 21B, the resistance Rch1 in the channelformation region is high; thus, influence of the resistance Rs betweenthe source region 909 s and the semiconductor layer 907 and theresistance Rd between the semiconductor layer 907 and the drain region909 d is ignorable.

However, in the thin film transistor with a channel length of 10 μm orless, preferably 5 μm or less in FIGS. 21C and 21D, the resistance Rch2in the channel formation region is low because the channel length L2 isshort; thus, influence of the resistance Rs between the source region909 s and the semiconductor layer 913 and the resistance Rd between thesemiconductor layer 913 and the drain region 909 d is not ignorable.

As a result, in the case where in the thin film transistor with achannel length of 10 μm or less, preferably 5 μm or less, the resistanceRs between the source region 909 s and the semiconductor layer 913 andthe resistance Rd between the semiconductor layer 913 and the drainregion 909 d are high, the amount of current flowing through the sourceregion, the semiconductor layer, and the drain region is reduced.Accordingly, an on current and field effect mobility are significantlyreduced.

Therefore, an object is to improve electric characteristics of aninverted-staggered thin film transistor.

According to an embodiment of the present invention, a gate electrodelayer, a semiconductor layer, a gate insulating layer between the gateelectrode layer and the semiconductor layer, source and drain regions incontact with the semiconductor layer, a source electrode layer incontact with the source region, and a drain electrode layer in contactwith the drain region are provided over a substrate. Further, the sourceand drain regions are formed using a microcrystalline semiconductorlayer to which an impurity imparting one conductivity type is added, andregions of the semiconductor layer, which are in contact with the sourceand drain regions, are formed of crystal regions. Further, the crystalregions in the semiconductor layer are not formed in a back channelregion and separated from each other; thus, they make a pair. Further,the semiconductor layer includes a semiconductor layer including anamorphous semiconductor.

Since the regions of the semiconductor layer, which are in contact withthe source and drain regions, are the pair of crystal regions,crystallinity at the interface between the semiconductor layer and thesource and drain regions is improved. Further, since semiconductormaterials are in contact with each other at the interface, latticeconstants are matched and there are insignificant distortion and fewdefects. Further, since the source and drain regions are formed using amicrocrystalline semiconductor layer to which an impurity imparting oneconductivity type is added, resistivity is low. Therefore, theresistance between the semiconductor layer and the source region and theresistance between the semiconductor layer and the drain region can bereduced. Further, the pair of crystal regions are separated by the backchannel region. Further, the semiconductor layer including an amorphoussemiconductor is in contact with the pair of crystal regions. Therefore,carriers flow in the semiconductor layer including an amorphoussemiconductor when the thin film transistor is off, so that an offcurrent can be reduced.

Alternatively, the semiconductor layer may have a three-layer structurein which a microcrystalline semiconductor layer, a semiconductor layerincluding an amorphous semiconductor, and a pair of crystal regions areformed on the side in contact with the gate insulating layer. Themicrocrystalline semiconductor layer is formed in a region of thesemiconductor layer, which is in contact with the gate insulating layer,so that crystallinity in a region through which carriers flow when thethin film transistor is on is excellent. Therefore, an on current andmobility of the thin film transistor can be increased.

Note that in the crystal regions in contact with the source and drainregions in the semiconductor layer, inverted conical or pyramidalcrystal grains are formed. Alternatively, columnar crystal grainsextending in the deposition direction are formed. Alternatively, in thecrystal regions, crystal grains are randomly formed.

Further, an on current refers to a current flowing between the sourceregion and the drain region, that is, through the channel formationregion when the thin film transistor is on (that is, when an appropriategate voltage is applied to the gate electrode layer in order that acurrent may flow through the channel formation region). Note that an onstate in this case refers to a state in which a gate voltage (thedifference between a potential of the gate electrode layer and apotential of the source region) exceeds the threshold voltage of thetransistor. Further, an off current refers to a current flowing betweenthe source region and the drain region, that is, through the channelformation region when the thin film transistor is off (that is, when thegate voltage of the thin film transistor is lower than the thresholdvoltage).

Crystallinity at the interface between the semiconductor layer formedover the gate insulating layer and the microcrystalline semiconductorlayer to which an impurity imparting one conductivity type is added isimproved, so that field effect mobility and an on current of the thinfilm transistor can be increased with an off current of the thin filmtransistor reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A and 1B are views each illustrating a structure of a thin filmtransistor according to an embodiment of the present invention;

FIGS. 2A to 2D are views each illustrating a structure of a thin filmtransistor according to an embodiment of the present invention;

FIGS. 3A and 3B are views each illustrating a structure of a thin filmtransistor according to an embodiment of the present invention;

FIGS. 4A and 4B are views each illustrating a structure of a thin filmtransistor according to an embodiment of the present invention;

FIG. 5 is a view illustrating a structure of a thin film transistoraccording to an embodiment of the present invention;

FIGS. 6A to 6C are views illustrating an example of a method formanufacturing a thin film transistor according to an embodiment of thepresent invention;

FIGS. 7A and 7B are views illustrating an example of a method formanufacturing a thin film transistor according to an embodiment of thepresent invention;

FIGS. 8A and 8B are diagrams each illustrating an example of a methodfor manufacturing a thin film transistor according to an embodiment ofthe present invention;

FIG. 9 is a time chart showing an example of a method for manufacturinga thin film transistor according to an embodiment of the presentinvention;

FIG. 10 is a time chart showing an example of a method for manufacturinga thin film transistor according to an embodiment of the presentinvention;

FIG. 11 is a time chart showing an example of a method for manufacturinga thin film transistor according to an embodiment of the presentinvention;

FIG. 12 is a time chart showing an example of a method for manufacturinga thin film transistor according to an embodiment of the presentinvention;

FIGS. 13A and 13B are views illustrating a method for manufacturing athin film transistor according to an embodiment of the presentinvention;

FIG. 14 is a time chart showing an example of a method for manufacturinga thin film transistor according to an embodiment of the presentinvention;

FIGS. 15A to 15C are views illustrating an example of a method formanufacturing a thin film transistor according to an embodiment of thepresent invention;

FIG. 16 is a time chart showing an example of a method for manufacturinga thin film transistor according to an embodiment of the presentinvention;

FIG. 17 is a time chart showing an example of a method for manufacturinga thin film transistor according to an embodiment of the presentinvention;

FIGS. 18A to 18C are views illustrating an example of a method formanufacturing a thin film transistor according to an embodiment of thepresent invention;

FIGS. 19A and 19B are views illustrating an example of a method formanufacturing a thin film transistor according to an embodiment of thepresent invention;

FIG. 20 is a view illustrating an example of a manufacturing method of athin film transistor according to an embodiment of the presentinvention;

FIGS. 21A and 21C are views each illustrating a structure of aconventional thin film transistor and FIGS. 21B and 21D are diagramseach illustrating an equivalent circuit thereof;

FIGS. 22A and 22B are views each illustrating a structure of a thin filmtransistor manufactured in Example 1;

FIG. 23 is a graph showing field effect mobility of a thin filmtransistor manufactured in Example 2;

FIG. 24 is a view illustrating an example of a display device includinga thin film transistor according to an embodiment of the presentinvention;

FIG. 25 is a view illustrating an example of a display device includinga thin film transistor according to an embodiment of the presentinvention; and

FIGS. 26A to 26D are diagrams each illustrating an electronic appliance.

DETAILED DESCRIPTION OF THE INVENTION

The embodiments and examples of the present invention to be disclosedwill be described with reference to the drawings. However, the presentinvention disclosed herein is not limited to the following descriptionbecause it will be easily understood by those skilled in the art thatvarious changes and modifications can be made to the modes and theirdetails without departing from the spirit and scope of the presentinvention disclosed herein. Therefore, the present invention disclosedherein should not be construed as being limited to the description inthe following embodiments and examples. Note that in describing astructure of the present invention disclosed herein with reference tothe drawings, common reference numerals are used for the same partsthroughout the drawings. Further, the same hatched patterns are appliedto the same parts, and the same parts are not especially denoted byreference numerals in some cases.

Embodiment 1

FIGS. 1A and 1B are cross-sectional views each illustrating a thin filmtransistor according to this embodiment. The thin film transistorillustrated in FIG. 1A includes, over a substrate 101, a gate electrodelayer 103, a semiconductor layer 129, a gate insulating layer 105between the gate electrode layer 103 and the semiconductor layer 129, asource region 127 s and a drain region 127 d which are in contact withthe semiconductor layer 129, a source electrode layer 125 s in contactwith the source region 127 s, and a drain electrode layer 125 d incontact with the drain region 127 d. The source region 127 s and thedrain region 127 d are formed using a microcrystalline semiconductorlayer to which an impurity imparting one conductivity type is added. Inthe semiconductor layer 129, regions in contact with the source region127 s and the drain region 127 d are formed of crystal regions 129 b and129 c. Further, the crystal regions 129 b and 129 c in the semiconductorlayer 129 are not formed in a back channel region and separated fromeach other; thus, they make a pair. Further, the semiconductor layer 129also includes a semiconductor layer 129 a including an amorphoussemiconductor.

The semiconductor layer 129 includes the semiconductor layer 129 aincluding an amorphous semiconductor, and the crystal regions 129 b and129 c. The semiconductor layer 129 a including an amorphoussemiconductor is formed on the gate insulating layer 105 side and thecrystal regions 129 b and 129 c are formed on the side of the sourceregion 127 s and the drain region 127 d. Further, the crystal regions129 b and 129 c are separated to form the pair of crystal regions, andthe semiconductor layer 129 a including an amorphous semiconductor isexposed between the pair of crystal regions 129 b and 129 c.

Further, the source region 127 s and the drain region 127 d are formedusing a microcrystalline semiconductor to which an impurity impartingone conductivity type is added and are in contact with the crystalregions 129 b and 129 c. Formation of a low density layer having manydefects and low density is suppressed at the interface between thesource and drain regions 127 s and 127 d and the crystal regions 129 band 129 c, and thus characteristics of the interface can be improved.Therefore, resistance at the interface between the source and drainregions 127 s and 127 d and the crystal regions 129 b and 129 c can bereduced. As a result, the amount of current flowing through the sourceregion, the semiconductor layer, and the drain region of the thin filmtransistor can be increased and an on current and field effect mobilitycan be increased.

Further, in the back channel region, since the crystal regions 129 b and129 c are separated and the semiconductor layer 129 a including anamorphous semiconductor is exposed, an off current flows through thesource region 127 s, the crystal region 129 b, the semiconductor layer129 a including an amorphous semiconductor with low resistivity, thecrystal region 129 c, and the drain region 127 d. Therefore, carriers donot easily flow in the semiconductor layer 129 a including an amorphoussemiconductor with low resistivity, so that an off current can bereduced.

In the semiconductor layer 129, the semiconductor layer 129 a includingan amorphous semiconductor can be formed using amorphous silicon,amorphous silicon germanium, amorphous silicon containing nitrogen,amorphous silicon germanium containing nitrogen, or the like. Thesemiconductor layer 129 a including an amorphous semiconductor is formedto a thickness of from 10 nm to 100 nm, preferably from 20 nm to 50 nm.

The crystal regions 129 b and 129 c included in the semiconductor layer129 are described with reference to FIGS. 2A to 2D. FIGS. 2A to 2D areenlarged views each illustrating a stack portion of the semiconductorlayer 129 a including an amorphous semiconductor, the crystal region 129b, and the source region 127 s.

As illustrated in FIG. 2A, the interface between the semiconductor layer129 a including an amorphous semiconductor and the crystal region 129 bcan be substantially plane. To form this structure, a microcrystallinesemiconductor may be formed as the crystal region 129 b over a surfaceof the semiconductor layer 129 a including an amorphous semiconductor.

Here, a microcrystalline semiconductor is a semiconductor having anintermediate structure between amorphous and crystalline structures(including a single crystal structure and a polycrystalline structure).A microcrystalline semiconductor is a semiconductor having a third statethat is stable in terms of free energy and is a crystallinesemiconductor having short-range order and lattice distortion, in whichcolumnar or needle-like crystals having a grain size of from 2 nm to 200nm, preferably from 10 nm to 80 nm, more preferably from 20 nm to 50 nmhave grown in a direction normal to the substrate surface. Therefore, acrystal grain boundary is formed at the interface of the columnar orneedle-like crystals in some cases (see FIG. 2A).

Further, the concentrations of oxygen and nitrogen contained in thecrystal region 129 b formed using a microcrystalline semiconductor,which are measured by secondary ion mass spectrometry, are preferablyless than 1×10¹⁸ atoms/cm³.

The Raman spectrum of the microcrystalline silicon which is a typicalexample of a microcrystalline semiconductor is shifted toward lowerwavenumber than 520 cm⁻¹ which represents the peak of the Raman spectrumof single crystal silicon. That is, a peak of the Raman spectrum ofmicrocrystalline silicon lies between 520 cm⁻¹ which represents that ofsingle crystal silicon, and 480 cm⁻¹ which represents that of amorphoussilicon. The semiconductor contains at least 1 atomic % of hydrogen orhalogen to terminate dangling bonds. Further, a rare gas element such ashelium, argon, krypton, or neon may be contained to further promotelattice distortion, so that stability is enhanced and a favorablemicrocrystalline semiconductor can be obtained. Such description about amicrocrystalline semiconductor is disclosed in, for example, U.S. Pat.No. 4,409,134.

Further, as illustrated in FIG. 2B, a structure can be obtained in whichthe low density regions 129 d are formed so that they are dispersed atthe interface of the semiconductor layer 129 a including an amorphoussemiconductor and the crystal region 129 b, and there are the interfaceat which the semiconductor layer 129 a including an amorphoussemiconductor and the crystal region 129 b are in contact with eachother and the interface at which the low density region 129 d is formedbetween the semiconductor layer 129 a including an amorphoussemiconductor and the crystal region 129 b.

As for the structure illustrated in FIGS. 2A and 2B, when the crystalregion 129 b is formed under the normal condition for depositing amicrocrystalline semiconductor, the low density region 129 d is alsoformed while the crystal region 129 b formed using a microcrystallinesemiconductor is formed in contact with the semiconductor layer 129 aincluding an amorphous semiconductor.

Further, as illustrated in FIG. 2C, the interface between thesemiconductor layer 129 a including an amorphous semiconductor and thecrystal region 129 b can be zigzagged. The microcrystallinesemiconductor having an inverted conical or pyramidal shape grows in athickness direction from a surface of the semiconductor layer 129 aincluding an amorphous semiconductor and adjacent crystal grains are incontact with each other on the source region 127 s side, so that theinterface between the semiconductor layer 129 a including an amorphoussemiconductor and the crystal region 129 b can be zigzagged asillustrated in FIG. 2C. That is to say, the interface between thesemiconductor layer 129 a including an amorphous semiconductor and thecrystal region 129 b becomes uneven.

The semiconductor layer 129 a including an amorphous semiconductor andthe crystal region 129 b which are illustrated in FIG. 2C are formed bymaking the semiconductor layer containing silicon, germanium, or silicongermanium as a main component contain nitrogen.

The crystal region 129 b is a crystal region in which inverted conicalor pyramidal crystal grains come in contact with each other. Here, in aninverted-staggered thin film transistor, an inverted conical orpyramidal shape refers to a three-dimensional shape formed of (i) a baseincluding a number of planes and (ii) lines connecting the periphery ofthe base and a vertex outside the base, in which the vertex is on thesubstrate 101 side. That is to say, the inverted conical or pyramidalshape is a shape growing in a direction in which the semiconductor layer129 a including an amorphous semiconductor and the crystal region 129 bare deposited in a substantially radial fashion. Each of crystal nucleiformed discretely grows in an orientation of the crystals at the sametime as the crystal region is formed, whereby crystal grains grow fromcrystal nuclei so as to spread in an in-plane direction of a planeperpendicular to a direction in which the crystal region 129 b isdeposited. The adjacent inverted conical or pyramidal crystal grainscome in contact with each other, whereby the crystal region is formed.Further, the crystal grain includes a single crystal or a twin crystal.

As for such crystal grains, the nitrogen concentration in thesemiconductor layer 129 a including an amorphous semiconductor is set tofrom 1×10²⁰ cm⁻³ to 1×10²¹ cm⁻³, preferably from 2×10²⁰ cm⁻³ to 1×10²¹cm⁻³, which is gradually reduced in a deposition direction up to from3×10²⁰ cm⁻³ to 1×10²¹ cm⁻³, whereby crystal nuclei are formed on asurface of the semiconductor layer 129 a including an amorphoussemiconductor, and crystal grains grow. Thus, the crystal region 129 bis formed.

Further, there is also a mode of the semiconductor layer 129 a includingan amorphous semiconductor in which microcrystal grains 129 e aredispersed as illustrated in FIG. 2D. The microcrystal grains 129 e aremicrocrystal grains which cannot become crystal growth nuclei of theinverted conical or pyramidal grains. The microcrystal grains eachtypically have a size of from 1 nm to 10 nm, preferably from 1 nm to 5nm. By controlling the nitrogen concentration in the semiconductor layer129 a including an amorphous semiconductor, the microcrystal grains canbe formed. Further, a large amount of nitrogen is likely to besegregated on the outside of the microcrystal grains, that is, on theside which is in contact with an amorphous structure. Therefore, a largeamount of nitrogen exists at the interface between the microcrystalgrain and the amorphous structure. Alternatively, a large number of NHgroups or NH₂ groups may exist at the interface between the microcrystalgrain and the amorphous structure.

Note that the microcrystal grains 129 e may be dispersed in theamorphous structure in the semiconductor layer 129 a including anamorphous semiconductor. Alternatively, the microcrystal grains may bemassed in the semiconductor layer 129 a including an amorphoussemiconductor. Still alternatively, dispersed microcrystal grains andmassed microcrystal grains may exist.

Owing to the microcrystal grains, resistance in a vertical direction ofthe semiconductor layer 129 a including an amorphous semiconductor, thatis, resistance between the semiconductor layer and the source region orthe drain region, can be reduced, whereby an on current of the thin filmtransistor can be increased.

A peak region of spectrum of the semiconductor layer 129 a including anamorphous semiconductor having any of such shapes illustrated in FIGS.2C and 2D, which is measured by low temperature photoluminescencespectroscopy, is from 1.31 eV to 1.39 eV. Further, the semiconductorlayer 129 a including an amorphous semiconductor has a steeper band tailslope of a band gap than an amorphous semiconductor typified byamorphous silicon. Therefore, the band gap becomes wide and thus atunnel current do not easily flow as compared to a conventionalamorphous semiconductor layer.

Note that as an impurity element which suppresses generation of crystalnuclei, oxygen and nitrogen can be given, and an impurity element (forexample, nitrogen) which is in silicon and does not trap carriers isselected. On the other hand, the concentration of an impurity element(for example, oxygen) which reduces the coordination number of siliconand generates dangling bonds is reduced. Therefore, it is preferable toreduce the oxygen concentration without reducing the nitrogenconcentration. Specifically, it is preferable that the oxygenconcentration measured by secondary ion mass spectrometry be 5×10¹⁸ cm⁻³or less.

Further, the semiconductor layer 129 a including an amorphoussemiconductor and the crystal region 129 b contain NH groups or NH₂groups in some cases. When NH groups are coupled to dangling bonds ofdifferent silicon atoms on the outside of the inverted conical orpyramidal microcrystal semiconductor, that is, at the interface betweenthe inverted conical or pyramidal crystal grain and the amorphousstructure, at the interface between the microcrystal grain and theamorphous structure, or in the dangling bond of an amorphoussemiconductor, defects are reduced, and carriers easily flow.Accordingly, a bonding which facilitates the carrier transfer is formedin a crystal grain boundary or a defect, whereby the mobility of thesilicon layer is increased. Accordingly, it is understood that themobility of the thin film transistor is increased. Note that as densityof the microcrystal grains is increased, crystallinity of thesemiconductor layer is increased; however, the crystal grain boundariesinterrupting carrier transfer are also increased. However, when thesilicon layer contains the NH group, and the dangling bond of adifferent Si is cross-linked, the bonding becomes a path for carriers atthe crystal grain boundary, whereby the carrier transfer is notinterrupted.

Further, when the dangling bond of the silicon atom is terminated by NH₂groups on the outside of the inverted conical or pyramidal microcrystalsemiconductor, that is, at the interface between the inverted conical orpyramidal crystal grain and the amorphous structure, at the interfacebetween the microcrystal grain and the amorphous structure, in thedangling bond of an amorphous semiconductor, generation of defect levelscan be prevented. If there is a defect level, electrons and holes aregenerated and recombined by thermal excitation through the defect level,whereby a Shockley-Read-Hall current flows. However, when there is nodefect level, the current can be reduced. Thus, by providing thesemiconductor layer 129 a including an amorphous semiconductorcontaining an NH₂ group in a region where an off current flows, the offcurrent can be reduced.

Further, by reducing the oxygen concentration in the semiconductorlayer, bonding which interrupts the carrier transfer in defects at theinterface between the microcrystal grain and the amorphous structure andat the interface between the microcrystal grains can be reduced.

For the source region 127 s and the drain region 127 d, amicrocrystalline semiconductor layer to which an impurity elementimparting one conductivity type is added is formed. In the case offorming an n-channel thin film transistor, phosphorus may be used as animpurity element imparting one conductivity type. The thin filmtransistor is typically formed using a microcrystalline silicon layerwhich contains phosphorus. In the case of forming a p-channel thin filmtransistor, boron may be used as an impurity element imparting oneconductivity type. The thin film transistor is typically formed using amicrocrystalline silicon layer which contains boron.

By setting the concentration of an impurity element imparting oneconductivity type, here, phosphorus or boron, to from 1×10¹⁹ cm⁻³ to1×10²¹ cm⁻³, an ohmic contact with a source electrode layer 125 s and adrain electrode layer 125 d can be obtained. Further, since the sourceregion 127 s and the drain region 127 d are formed using amicrocrystalline semiconductor layer, resistance of the source region127 s and the drain region 127 d can be reduced.

The source region 127 s and the drain region 127 d are formed to have athickness of from 5 nm to 50 nm, preferably, from 10 nm to 30 nm. Byreducing the thickness of the source region 127 s and the drain region127 d, throughput can be increased. Further, by reducing the thicknessof the source region 127 s and the drain region 127 d, stress can bereduced; thus, peeling at the source region 127 s and the drain region127 d can be prevented.

Further, as illustrated in FIG. 1B, a microcrystalline semiconductorlayer 131 may be formed between the gate insulating layer 105 and thesemiconductor layer 129, that is, between the gate insulating layer 105and the semiconductor layer 129 a including an amorphous semiconductor.

Note that in the case of forming the semiconductor layer 129 a includingan amorphous semiconductor over the microcrystalline semiconductor layer131, there is a case where in an early stage of deposition, crystalsgrow to have conical or pyramidal shapes by using the microcrystallinesemiconductor layer 131 as a seed crystal, so that a surface of themicrocrystalline semiconductor layer 131 becomes uneven. That is to say,when the interface between the microcrystalline semiconductor layer 131and the semiconductor layer 129 a including an amorphous semiconductoris uneven, the barrier at the interface between the microcrystallinesemiconductor layer 131 and the semiconductor layer 129 a including anamorphous semiconductor can be low and thus, an on current and fieldeffect mobility can be increased.

In the thin film transistor, an on current flows in a semiconductorlayer in contact with the gate insulating layer 105 and in the vicinityof the gate insulating layer 105. Therefore, by forming themicrocrystalline semiconductor layer 131 over the gate insulating layer105, crystallinity can be improved and resistivity can be reduced ascompared to the semiconductor layer 129 a including an amorphoussemiconductor, so that an on current easily flows. Accordingly, an oncurrent and field effect mobility of the thin film transistor can befurther increased.

As the substrate 101, a glass substrate, a ceramic substrate, or aplastic substrate or the like with heat resistance which can withstand aprocess temperature in this manufacturing process can be used. In thecase where the substrate does not need a light-transmitting property, asubstrate obtained by providing an insulating layer on a surface of asubstrate of a metal such as a stainless steel alloy may be used. As aglass substrate, for example, an alkali-free glass substrate of bariumborosilicate glass, aluminoborosilicate glass, aluminosilicate glass, orthe like may be used.

The gate electrode layer 103 can be formed to have a single-layerstructure or a layered structure using a metal material such asmolybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper,neodymium, or scandium or an alloy material which contains any of thesematerials as its main component. Alternatively, a semiconductor layertypified by polycrystalline silicon doped with an impurity element suchas phosphorus, or an AgPdCu alloy may be used.

For example, as a two-layer structure of the gate electrode layer 103, atwo-layer structure in which a molybdenum layer is stacked over analuminum layer, a two-layer structure in which a molybdenum layer isstacked over a copper layer, a two-layer structure in which a titaniumnitride layer or a tantalum nitride layer is stacked over a copperlayer, or a two-layer structure in which a titanium nitride layer and amolybdenum layer are stacked is preferable. As a three-layer structure,a structure in which a tungsten layer or a tungsten nitride layer, alayer of an alloy of aluminum and silicon or an alloy of aluminum andtitanium, and a titanium nitride layer or a titanium layer are stackedis preferable. When a metal layer serving as a barrier layer is stackedover a layer with low electric resistance, a metal element can beprevented from diffusing from the layer with low electric resistanceinto the semiconductor layer.

The gate insulating layer 105 can be formed to have a single-layerstructure or a layered structure using any of a silicon oxide layer, asilicon nitride layer, a silicon oxynitride layer, and a silicon nitrideoxide layer by a CVD method, a sputtering method, or the like. Byforming the gate insulating layer 105 using a silicon oxide layer or asilicon oxynitride layer, in the case of forming the microcrystallinesemiconductor layer 131 over the gate insulating layer 105 asillustrated in FIG. 1B, fluctuation in threshold voltage of the thinfilm transistor can be reduced.

Note that in this specification, silicon oxynitride contains more oxygenthan nitrogen and, in the case where measurements are performed usingRutherford backscattering spectrometry (RBS) and hydrogen forwardscattering (HFS), contains oxygen, nitrogen, silicon, and hydrogen atconcentrations of 50 to 70 at. %, 0.5 to 15 at. %, 25 to 35 at. %, and0.1 to 10 at. %, respectively. Further, silicon nitride oxide containsmore nitrogen than oxygen and, in the case where measurements areperformed using RBS and HFS, contains oxygen, nitrogen, silicon, andhydrogen at concentrations of 5 to 30 at. %, 20 to 55 at. %, 25 to 35at. %, and 10 to 30 at. %, respectively. Note that percentages ofnitrogen, oxygen, silicon, and hydrogen fall within the ranges givenabove, where the total number of atoms contained in the siliconoxynitride or the silicon nitride oxide is defined as 100 at. %.

The source electrode layer 125 s and the drain electrode layer 125 d canbe formed to have a single-layer structure or a layered structure usingany of aluminum, copper, titanium, neodymium, scandium, molybdenum,chromium, tantalum, tungsten, and the like. Alternatively, an aluminumalloy to which an element to prevent a hillock is added (for example, analuminum-neodymium alloy which can be used for the gate electrode layer103) may be used. Alternatively, a crystalline silicon layer to which animpurity element serving as a donor is added may be used. The sourceelectrode layer 125 s and the drain electrode layer 125 d may have alayered structure in which a layer on the side in contact with thecrystalline silicon layer to which an impurity element serving as adonor is added is formed using titanium, tantalum, molybdenum, tungsten,or a nitride of any of these elements and aluminum or an aluminum alloyis formed thereover. Alternatively, another layered structure may beemployed in which a top surface and a bottom surface of a layer ofaluminum or an aluminum alloy are sandwiched between titanium, tantalum,molybdenum, tungsten, or a nitride of any of these elements. Forexample, the source electrode layer 125 s and the drain electrode layer125 d preferably have a three-layer structure in which an aluminum layeris sandwiched between molybdenum layers.

According to this embodiment, field effect mobility and an on current ofthe thin film transistor can be increased with an off current of thethin film transistor reduced. In particular, in the thin film transistorin which a channel length is 10 μm or less, typically, from 2 μm to 5μm, resistance between the semiconductor layer and the source and drainregions 127 s and 127 d can be reduced, so that an on current andmobility of the thin film transistor can be increased.

Embodiment 2

This embodiment will describe a structure of a semiconductor layer inwhich crystallinity of the interface between the semiconductor layer 129a including an amorphous semiconductor and the crystal regions 129 b and129 c can be improved with reference to FIGS. 3A and 3B and 4A and 4B.

FIG. 3A illustrates the thin film transistor in FIG. 1A described inEmbodiment 1 in which semiconductor layers 137 a and 137 b eachcontaining a halogen element are additionally provided at the interfacebetween the semiconductor layer 129 a including an amorphoussemiconductor and the crystal regions 129 b and 129 c.

The semiconductor layers 137 a and 137 b each containing a halogenelement are formed using microcrystalline silicon containing fluorine orchlorine or microcrystalline silicon germanium containing fluorine orchlorine.

FIGS. 4A and 4B are enlarged views each illustrating a stack portion ofthe semiconductor layer 129 a including an amorphous semiconductor, thesemiconductor layer 137 a containing a halogen element, the crystalregion 129 b, and the source region 127 s.

As illustrated in FIG. 4A, the interfaces between the semiconductorlayer 129 a including an amorphous semiconductor and the semiconductorlayer 137 a containing a halogen element and between the semiconductorlayer 137 a containing a halogen element and the crystal region 129 bcan be substantially plane. To form this structure, a microcrystallinesemiconductor may be formed as the crystal region 129 b on a surface ofthe semiconductor layer 137 a containing a halogen element.

Further, as illustrated in FIG. 4B, a structure can be obtained in whichthe low density regions 129 d are formed to be separated at theinterface between the semiconductor layer 137 a containing a halogenelement and the crystal region 129 b, and there are the interface atwhich the semiconductor layer 137 a containing a halogen element and thecrystal region 129 b are in contact with each other and the interface atwhich the low density region 129 d is formed between the semiconductorlayer 137 a containing a halogen element and the crystal region 129 b.

In the case of forming a semiconductor layer over the semiconductorlayers 137 a and 137 b each containing a halogen element, thesemiconductor layer can be formed to include a small amount of amorphoussemiconductor and have excellent crystallinity owing to thesemiconductor layers 137 a and 137 b each containing a halogen element.Accordingly, by using the semiconductor layers 137 a and 137 b eachcontaining a halogen element as seed crystals, the crystal regions 129 band 129 c are formed without including a low density layer at theinterface between the semiconductor layers 137 a and 137 b eachcontaining a halogen element. Further, by using the crystal regions 129b and 129 c as seed crystals, a microcrystalline semiconductor layer towhich an impurity element imparting one conductivity type is added isformed.

Since the proportion of the low density layer with high resistivity isreduced at the interface between the source and drain regions 127 s and127 d and the crystal regions 129 b and 129 c, resistance in the regionscan be reduced. Accordingly, the amount of current flowing through thesource region, the semiconductor layer, and the drain region of the thinfilm transistor can be increased and an on current and field effectmobility can be increased.

Further, as illustrated in FIG. 3B, the microcrystalline semiconductorlayer 131 may be formed between the gate insulating layer 105 and thesemiconductor layer 129, that is, between the gate insulating layer 105and the semiconductor layer 129 a including an amorphous semiconductorin a manner similar to that of FIG. 1B.

In the thin film transistor, an on current flows in a semiconductorlayer in contact with the gate insulating layer 105 and in the vicinityof the gate insulating layer 105. Therefore, by forming themicrocrystalline semiconductor layer 131 over the gate insulating layer105, crystallinity can be improved and resistivity can be reduced ascompared to the semiconductor layer 129 a including an amorphoussemiconductor, so that an on current easily flows. Accordingly, an oncurrent and field effect mobility of the thin film transistor can befurther increased.

Embodiment 3

This embodiment will describe a structure applicable to Embodiments 1and 2 with reference to FIG. 5.

Embodiments 1 and 2 describe the thin film transistor in which thesource electrode layer 125 s and the drain electrode layer 125 d are incontact with the source region 127 s and the drain region 127 d,respectively, but are not in contact with the semiconductor layer 129.The thin film transistor in this embodiment includes a source electrodelayer 133 s in contact with the source region 127 s, the semiconductorlayer 129 a including an amorphous semiconductor, and the crystal region129 b and a drain electrode layer 133 d in contact with the drain region127 d, the semiconductor layer 129 a including an amorphoussemiconductor, and the crystal region 129 c, instead of the sourceelectrode layer 125 s and the drain electrode layer 125 d.

Note that in FIG. 5, end portions of the source electrode layer 133 sand the drain electrode layer 133 d and end portions of the sourceregion 127 s and the drain region 127 d are aligned respectively;however, the present invention is not limited thereto. The end portionsof the source electrode layer 133 s and the source region 127 s may bemisaligned and the source region 127 s may be exposed. Similarly, theend portions of the drain electrode layer 133 d and the drain region 127d may be misaligned and the drain region 127 d may be exposed.

Embodiment 4

This embodiment will describe a method for manufacturing a thin filmtransistor described in Embodiment 1 with reference to FIGS. 6A to 6Cand 7A and 7B. An n-channel thin film transistor has higher carriermobility than a p-channel thin film transistor, and it is preferablethat all thin film transistors formed over the same substrate have thesame polarity because the number of manufacturing steps can be reduced.Therefore, in this embodiment, a method for manufacturing an n-channelthin film transistor will be described.

The gate electrode layer 103 is formed over the substrate 101. Then, thegate insulating layer 105, a semiconductor layer 107, a microcrystallinesemiconductor layer 109 to which an impurity imparting one conductivitytype is added, and a conductive layer 111 are formed so as to cover thegate electrode layer 103. After that, a resist mask 113 is formed overthe conductive layer 111 (see FIG. 6A).

As the substrate 101, the substrate 101 described in Embodiment 1 can beused as appropriate.

The gate electrode layer 103 is formed using a material used for thegate electrode layer 103 described in Embodiment 1 as appropriate. Thegate electrode layer 103 can be formed in such a manner that aconductive layer is formed over the substrate 101 with the use of theabove material by a sputtering method or a vacuum evaporation method, amask is formed over the conductive layer by a photolithography method,an ink-jet method, or the like, and the conductive layer is etched usingthe mask. Alternatively, the gate electrode layer 103 can be formed bydischarging a conductive nanopaste of silver, gold, copper, or the likeover the substrate by an ink-jet method and baking the conductivenanopaste. Note that a nitride layer of any of the above metal materialsmay be provided between the substrate 101 and the gate electrode layer103 as barrier metal in order to increase adhesion between the gateelectrode layer 103 and the substrate 101. Here, a conductive layer isformed over the substrate 101 and then etched using a resist mask formedusing a photomask.

Note that it is preferable that side surfaces of the gate electrodelayer 103 have tapered shapes so that disconnection of the semiconductorlayer and the wiring layer formed over the gate electrode layer 103 inthe later step at a step portion can be prevented. In order to form theside surfaces of the gate electrode layer 103 to have tapered shapes,etching may be performed while the resist mask is made to recede.

Through the step of forming the gate electrode layer 103, a gate wiring(a scan line) and the capacitor wiring can also be formed at the sametime. Note that a “scan line” means a wiring which selects a pixel,while a “capacitor wiring” means a wiring which is connected to one ofelectrodes of a storage capacitor in a pixel. However, withoutlimitation thereto, the gate electrode layer 103 and one or both of agate wiring and a capacitor wiring may be formed separately.

The gate insulating layer 105 can be formed using any of the materialsfor the gate insulating layer 105 described in Embodiment 1 asappropriate. The gate insulating layer 105 can be formed by a CVDmethod, a sputtering method, or the like. Further, the gate insulatinglayer 105 may be formed using a microwave plasma CVD apparatus with ahigh frequency (1 GHz or more). By forming the gate insulating layer 105by a microwave plasma CVD apparatus with a high frequency, the withstandvoltage between a gate electrode layer and source and drain electrodelayers can be improved; therefore, a highly reliable thin filmtransistor can be obtained. Further, by forming a silicon oxide layer asthe gate insulating layer 105 by a CVD method using an organosilane gas,the amount of hydrogen contained in the gate insulating layer can bereduced and fluctuation in threshold voltage of the thin film transistorcan be reduced. As the organosilane gas, a silicon-containing compoundsuch as tetraethoxysilane (TEOS) (chemical formula: Si(OC₂H₅)₄),tetramethylsilane (TMS) (chemical formula. Si(CH₃)₄),tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane(OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC₂H₅)₃), ortrisdimethylaminosilane (SiH(N(CH₃)₂)₃) can be used.

For the semiconductor layer 107, a semiconductor layer 107 a includingan amorphous semiconductor and a crystal region 107 b are formed. Thesemiconductor layer 107 a including an amorphous semiconductor is formedusing amorphous silicon, amorphous silicon germanium, or the like. Thesemiconductor layer 107 a including an amorphous semiconductor is formedto a thickness of from 10 nm to 100 nm, preferably from 20 nm to 50 nm.

In a treatment chamber of a plasma CVD apparatus, a deposition gascontaining silicon or germanium is introduced and an amorphoussemiconductor layer is formed by glow discharge plasma as thesemiconductor layer 107 a including an amorphous semiconductor.Alternatively, a deposition gas containing silicon or germanium isdiluted with one or plural kinds of rare gas elements selected fromhelium, argon, krypton, and neon, and an amorphous semiconductor layeris formed by glow discharge plasma. Still alternatively, a depositiongas containing silicon or germanium and hydrogen with a flow rate of 1to 10 times, preferably 1 to 5 times as high as that of the depositiongas are mixed, and an amorphous semiconductor layer is formed by glowdischarge plasma. Note that a halogen such as fluorine or chlorine,nitrogen, or the like may be added to the semiconductor layer 107 aincluding an amorphous semiconductor.

As typical examples of the deposition gas containing silicon orgermanium, SiH₄, Si₂H₆, GeH₄, and Ge₂H₆ are given.

Note that before the semiconductor layer 107 a including an amorphoussemiconductor is formed, impurity elements in the treatment chamber ofthe CVD apparatus are removed by introducing a deposition gas containingsilicon or germanium with the air in the treatment chamber exhausted, sothat impurities at the interface between the gate insulating layer 105and the semiconductor layer 107 a including an amorphous semiconductorof the thin film transistor to be formed later can be reduced and thus,electric characteristics of the thin film transistor can be improved.

The crystal region 107 b is formed using microcrystalline silicon,microcrystalline silicon germanium, or the like. The crystal region 107b is formed to a thickness of from 10 nm to 100 nm, preferably from 30nm to 50 nm. In the treatment chamber of the plasma CVD apparatus, adeposition gas containing silicon or germanium is mixed with hydrogen,and the crystal region 107 b is formed by glow discharge plasma. Themicrocrystalline silicon, the microcrystalline silicon germanium, or thelike is formed using a mixture of the deposition gas containing siliconor germanium and hydrogen, which is obtained by diluting the depositiongas with hydrogen whose flow rate is 10 to 2000 times, preferably 50 to200 times that of the deposition gas.

The microcrystalline semiconductor layer 109 to which an impurityimparting one conductivity type is added is formed usingmicrocrystalline silicon to which phosphorus is added, microcrystallinesilicon germanium to which phosphorus is added, microcrystallinegermanium to which phosphorus is added, or the like. Themicrocrystalline semiconductor layer 109 to which an impurity impartingone conductivity type is added is formed to a thickness of from 5 nm to50 nm, preferably from 10 nm to 30 nm. In the treatment chamber of theplasma CVD apparatus, a deposition gas containing silicon or germanium,hydrogen, and phosphine (diluted with hydrogen or silane) are mixed andthe microcrystalline semiconductor layer 109 to which an impurityimparting one conductivity type is added is formed by glow dischargeplasma. The microcrystalline silicon to which phosphorus is added, themicrocrystalline silicon germanium to which phosphorus is added, themicrocrystalline germanium to which phosphorus is added, or the like isformed using a mixture of the deposition gas containing silicon orgermanium and hydrogen, which is obtained by diluting the deposition gaswith hydrogen with a flow rate of 10 to 2000 times, preferably 50 to 200times as high as that of the deposition gas.

Further, in the case of forming a p-channel thin film transistor, themicrocrystalline semiconductor layer 109 to which an impurity impartingone conductivity type is added is formed by a plasma CVD method using adeposition gas containing silicon or germanium, diborane, and hydrogen.

In the steps for forming the semiconductor layer 107 a including anamorphous semiconductor, the crystal region 107 b, and themicrocrystalline semiconductor layer 109 to which an impurity impartingone conductivity type is added, glow discharge plasma is generated byapplying high-frequency power with a frequency of 3 MHz to 30 MHz,typically 13.56 MHz or 27.12 MHz, or high-frequency power with afrequency in the VHF band of over 30 MHz up to about 300 MHz, typically60 MHz.

First, the substrate 101 over which the gate electrode layer 103 isformed is heated in the treatment chamber of the CVD apparatus, and inorder to form a silicon nitride layer as the gate insulating layer 105,source gases for forming the silicon nitride layer are introduced intothe treatment chamber (pretreatment 201 in FIG. 9). Here, for example, asilicon nitride layer with a thickness of about 110 nm is formed in sucha manner that the source gases are introduced and stabilized, where theflow rate of SiH₄ is 40 sccm, the flow rate of H₂ is 500 sccm, the flowrate of N₂ is 550 sccm, and the flow rate of NH₃ is 140 sccm, and plasmadischarge with an output of 370 W is performed, where the pressure inthe treatment chamber is 100 Pa and the temperature of the substrate is280° C. After that, only the supply of SiH₄ is stopped, and afterseveral seconds, the plasma discharge is stopped (formation of SiN 203in FIG. 9). This is because if plasma discharge is stopped in a statewhere SiH₄ is present in the treatment chamber, grains or particlescontaining silicon as the main component are formed, which causesreduction in yield.

Through the above steps, the gate insulating layer 105 can be formed.After the gate insulating layer 105 is formed, the source gases used fordepositing the silicon nitride layer are exhausted, and the substrate101 is carried out of the treatment chamber (unload 206 in FIG. 9).

Next, a source gas for forming an amorphous silicon layer as aprotective layer is introduced into the treatment chamber and treatmentfor forming the amorphous silicon layer in the treatment chamber isperformed (precoating treatment 207 in FIG. 9). By coating the innerwall of treatment chamber with the amorphous silicon layer, it ispossible to prevent an impurity attached to the inner wall of thetreatment chamber, an element for forming the inner wall of thetreatment chamber, or the silicon nitride layer formed as the gateinsulating layer from being mixed into the semiconductor layer 107 aincluding an amorphous semiconductor to be formed later. Although theamorphous silicon layer is formed using only SiH₄ here in order toincrease the deposition rate of the amorphous silicon layer, hydrogenmay also be introduced into the treatment chamber as shown by a dashedline of the precoating treatment 207 in FIG. 9.

After that, the substrate 101 is carried into the treatment chamber, andsource gases for depositing an amorphous silicon layer as thesemiconductor layer 107 a including an amorphous semiconductor isintroduced into the treatment chamber (load 208 in FIG. 9).

Next, an amorphous silicon layer is formed as the semiconductor layer107 a including an amorphous semiconductor over an entire surface of thegate insulating layer 105. First, source gases for forming the amorphoussilicon layer as the semiconductor layer 107 a including an amorphoussemiconductor are introduced into the treatment chamber. Here, forexample, an amorphous silicon layer with a thickness of about 50 nm isformed in such a manner that the source gases are introduced andstabilized, where the flow rate of SiH₄ is 280 sccm and the flow rate ofH₂ is 300 sccm, and plasma discharge with an output of 60 W isperformed, where the pressure in the treatment chamber is 170 Pa and thetemperature of the substrate is 280° C. After that, in a manner similarto that of formation of the silicon nitride layer described above, onlythe supply of SiH₄ is stopped, and after several seconds, the plasmadischarge is stopped (formation of a-Si 211 in FIG. 9).

Next, a microcrystalline silicon layer is formed as the crystal region107 b over an entire surface of the semiconductor layer 107 a includingan amorphous semiconductor. First, source gases for forming themicrocrystalline silicon layer as the crystal region 107 b areintroduced into the treatment chamber. Here, for example, amicrocrystalline silicon layer with a thickness of about 50 nm is formedin such a manner that the source gases are introduced and stabilized,where the flow rate of SiH₄ is 10 sccm and the flow rate of H₂ is 1500sccm, and plasma discharge with an output of 50 W is performed, wherethe pressure in the treatment chamber is 280 Pa and the temperature ofthe substrate is 280° C. After that, in a manner similar to that offormation of the silicon nitride layer or the like described above, onlythe supply of SiH₄ is stopped, and after several seconds, the plasmadischarge is stopped (formation of crystal region 215 in FIG. 9).

Next, the microcrystalline semiconductor layer 109 to which an impurityimparting one conductivity type is added is formed over an entiresurface of the crystal region 107 b. First, source gases for forming amicrocrystalline silicon layer to which phosphorus is added as themicrocrystalline semiconductor layer 109 to which an impurity impartingone conductivity type is added are introduced into the treatmentchamber. Here, for example, a semiconductor layer with a thickness ofabout 50 nm is formed in such a manner that the source gases areintroduced and stabilized, where the flow rate of SiH₄ is 10 sccm, theflow rate of a mixed gas in which PH₃ is diluted with H₂ to 0.5 vol % is30 secm, and the flow rate of hydrogen is 1500 sccm, and plasmadischarge with an output of 300 W is performed, where the pressure inthe treatment chamber is 280 Pa and the temperature of the substrate is280° C. After that, in a manner similar to that of formation of thesilicon nitride layer or the like described above, only the supply ofSiH₄ is stopped, and after several seconds, the plasma discharge isstopped (formation of impurity semiconductor layer 219 in FIG. 9). Afterthat, these gases are exhausted (exhaust 221 in FIG. 9).

As described above, layers from the gate insulating layer 105 to themicrocrystalline semiconductor layer 109 to which an impurity impartingone conductivity type is added can be formed (see FIG. 6A).

In this embodiment, since the microcrystalline semiconductor layer 109to which an impurity imparting one conductivity type is added is formedover the crystal region 107 b, crystal growth of the microcrystallinesemiconductor layer 109 to which an impurity imparting one conductivitytype is added occurs using the crystals of the surface of the crystalregion 107 b as seed crystals. Therefore, formation of a low densitylayer in an early stage of the deposition can be suppressed.

The conductive layer 111 can be formed using a material and a layeredstructure of the source electrode layer 125 s and the drain electrodelayer 125 d described in Embodiment 1 as appropriate. The conductivelayer 111 is formed by a CVD method, a sputtering method, or a vacuumevaporation method. Alternatively, the conductive layer 111 may beformed by discharging a conductive nanopaste of silver, gold, copper, orthe like by a screen printing method, an ink-jet method, or the like andbaking the conductive nanopaste. After that a second resist mask isformed over the conductive layer 111.

The resist mask 113 has two regions with different thicknesses and canbe formed using a multi-tone mask. The multi-tone mask is used, so thatthe number of photomasks to be used and the number of manufacturingsteps are reduced, which is preferable. In this embodiment, themulti-tone mask can be used in a step of forming a pattern of thesemiconductor layer and a step of separating the semiconductor layerinto a source region and a drain region.

A multi-tone mask is a mask capable of light exposure with multi-levelamount of light, and typically, light exposure is performed with threelevels of light amount to provide an exposed region, a half-exposedregion, and an unexposed region. When the multi-tone mask is used,one-time light exposure and development process allow a resist mask withplural thicknesses (typically, two kinds of thicknesses) to be formed.Therefore, by using a multi-tone mask, the number of photomasks can bereduced.

FIGS. 8A-1 and 8B-1 are cross-sectional views of typical multi-tonemasks. FIG. 8A-1 illustrates a gray-tone mask 180 and FIG. 8B-1illustrates a half-tone mask 185.

The gray-tone mask 180 illustrated in FIG. 8A-1 includes alight-blocking portion 182 formed using a light-blocking layer on asubstrate 181 having a light-transmitting property, and a diffractiongrating portion 183 provided with a pattern of the light-blocking layer.

The diffraction grating portion 183 has slits, dots, mesh, or the likethat is provided at intervals which are less than or equal to theresolution limit of light used for the exposure, whereby the lighttransmittance can be controlled. Note that the slits, dots, or meshprovided at the diffraction grating portion 183 may be providedperiodically or non-periodically.

As the substrate 181 having a light-transmitting property, a quartzsubstrate or the like can be used. The light-blocking layer for formingthe light-blocking portion 182 and the diffraction grating portion 183may be formed using metal, preferably, chromium, chromium oxide, or thelike.

In the case where the gray-tone mask 180 is irradiated with light forlight exposure, as illustrated in FIG. 8A-2, the transmittance in theregion overlapping with the light-blocking portion 182 is 0%, and thetransmittance in the region where both the light-blocking portion 182and the diffraction grating portion 183 are not provided is 100%.Further, the transmittance at the diffraction grating portion 183 isapproximately in the range of 10 to 70%, which can be adjusted by theinterval of slits, dots, or mesh of the diffraction grating, or thelike.

The half-tone mask 185 illustrated in FIG. 8B-1 includes asemi-light-transmitting portion 187 which is formed on a substrate 186having a light-transmitting property, using a semi-light-transmittinglayer, and a light-blocking portion 188 formed using a light-blockinglayer.

The semi-light-transmitting portion 187 can be formed using a layer ofMoSiN, MoSi, MoSiO, MoSiON, CrSi, or the like. The light-blockingportion 188 may be formed using metal similar to that used for thelight-blocking layer of the gray-tone mask, preferably, chromium,chromium oxide, or the like.

In the case where the half-tone mask 185 is irradiated with light forlight exposure, as illustrated in FIG. 8B-2, the transmittance in theregion overlapping with the light-blocking portion 188 is 0%, and thetransmittance in the region where both the light-blocking portion 188and the semi-light-transmitting portion 187 are not provided is 100%.Further, the transmittance in the semi-light-transmitting portion 187 isapproximately in the range of 10 to 70%, which can be adjusted by thekind, the thickness, or the like of the material to be used.

By light exposure using the multi-tone mask and development, a resistmask which has regions having different thicknesses can be formed.

Next, with the use of the resist mask 113, the semiconductor layer 107,the microcrystalline semiconductor layer 109 to which an impurityimparting one conductivity type is added, and the conductive layer 111are etched. Through this step, the semiconductor layer 107, themicrocrystalline semiconductor layer 109 to which an impurity impartingone conductivity type is added, and the conductive layer 111 areseparated for each element to form a semiconductor layer 115, themicrocrystalline semiconductor layer 117 to which an impurity impartingone conductivity type is added, and the conductive layer 119 (FIG. 6B).

Next, the resist mask 113 is made to recede to form a separated resistmasks 123. Ashing using oxygen plasma may be performed in order that theresist mask may be made to recede. Here, ashing is performed on theresist mask 113 so that the resist mask 113 is separated over the gateelectrode layer. As a result, the resist masks 123 can be formed (FIG.6C).

Next, with the use of the resist masks 123, the conductive layer 119 isetched to form the source electrode layer 125 s and the drain electrodelayer 125 d (see FIG. 7A). The conductive layer 119 is preferably etchedby wet etching. By wet etching, the conductive layer is etchedisotropically. As a result, the conductive layer recedes so that it ison an inner side than the resist mask 123, and thus the source electrodelayer 125 s and the drain electrode layer 125 d are formed. The sourceelectrode layer 125 s and the drain electrode layer 125 d serve not onlyas a source electrode layer and a drain electrode layer but also assignal lines. However, without limitation thereto, signal lines may beprovided separately from the source electrode layer 125 s and the drainelectrode layer 125 d.

Next, with the use of the resist mask 123, a semiconductor layer 115 aincluding an amorphous semiconductor, a crystal region 115 b, and amicrocrystalline semiconductor layer 117 to which an impurity impartingone conductivity type is added are partly etched. Here, dry etching isemployed. The semiconductor layer 129 a including an amorphoussemiconductor, the crystal regions 129 b and 129 c, the source region127 s, and the drain region 127 d are formed through the process up tothis step. After that, the resist mask 123 is removed (see FIG. 7B).

Note that here, the conductive layer 119 is wet-etched and thesemiconductor layer 115 a including an amorphous semiconductor, thecrystal region 115 b, and the microcrystalline semiconductor layer 117to which an impurity imparting one conductivity type is added arc partlydry-etched. Accordingly, the conductive layer 119 is isotropicallyetched, and side surfaces of the source electrode layer 125 s and thedrain electrode layer 125 d are not aligned with side surfaces of thesource region 127 s and the drain region 127 d, so that the sidesurfaces of the source region 127 s and the drain region 127 d are onouter sides than the side surfaces of the source electrode layer 125 sand the drain electrode layer 125 d.

Next, dry etching is preferably performed after the resist mask 123 isremoved. A condition of dry etching is set so that the exposed region ofthe semiconductor layer 129 a including an amorphous semiconductor isnot damaged and the etching rate with respect to the semiconductor layer129 a including an amorphous semiconductor is low. In other words, acondition which gives almost no damages to the exposed surface of thesemiconductor layer 129 a including an amorphous semiconductor andhardly reduces the thickness of the exposed region of the semiconductorlayer 129 a including an amorphous semiconductor is applied. As anetching gas, a chlorine-based gas, typically, Cl₂, CF₄, N₂, or the likeis used. There is no particular limitation on an etching method and aninductively coupled plasma (ICP) method, a capacitively coupled plasma(CCP) method, an electron cyclotron resonance (ECR) method, or areactive ion etching (RIE) method, or the like can be used.

Next, the surface of the semiconductor layer 129 a including anamorphous semiconductor may be irradiated with water plasma, ammoniaplasma, nitrogen plasma, or the like.

Water plasma treatment can be performed in such a manner that a gascontaining water as its main component typified by water vapor (H₂Ovapor) is introduced into a reaction space to generate plasma.

As described above, after the source region 127 s and the drain region127 d are formed, dry etching is further performed under such acondition that the semiconductor layer 129 a including an amorphoussemiconductor is not damaged, whereby an impurity element such as aresidue existing on the exposed region of the semiconductor layer 129 aincluding an amorphous semiconductor can be removed. Further, after dryetching, water plasma treatment is performed, whereby a residue of theresist mask can also be removed. By water plasma treatment, insulationbetween the source region and the drain region can be secured, and thus,in a thin film transistor which is completed, an off current can bereduced, and variation in electric characteristics can be reduced.

Through the above process, a thin film transistor with high field effectmobility, a large on current, and a small off current can bemanufactured by using a small number of masks.

Embodiment 5

This embodiment will describe a formation method which can be employedinstead of the method for forming the gate insulating layer 105, thesemiconductor layer 107 a including an amorphous semiconductor, and thecrystal region 107 b in Embodiment 4.

Here, a process for forming a silicon nitride layer as the gateinsulating layer 105, an amorphous silicon layer containing nitrogen asthe semiconductor layer 107 a including an amorphous semiconductor, aninverted conical or pyramidal microcrystalline silicon layer as thecrystal region 107 b, and a microcrystalline silicon layer containingphosphorus as the microcrystalline semiconductor layer 109 to which animpurity imparting one conductivity type is added will be described withreference to a time chart shown in FIG. 10.

First, the substrate 101 over which the gate electrode layer 103 isformed is heated in a treatment chamber of a CVD apparatus, and in orderto form a silicon nitride layer as the gate insulating layer 105, sourcegases used for depositing a silicon nitride layer are introduced intothe treatment chamber (pretreatment 201 in FIG. 10). Here, a siliconnitride layer with a thickness of about 110 nm is formed in a mannersimilar to that of formation of SiN 203 described in Embodiment 4. Afterthat, only the supply of SiH₄ is stopped, and after several seconds, theplasma discharge is stopped (formation of SiN 203 in FIG. 10). Throughthe above steps, the gate insulating layer 105 can be formed.

Next, the source gases used for depositing the silicon nitride layer areexhausted and source gases used for forming the semiconductor layer 107a including an amorphous semiconductor are introduced into the treatmentchamber (replacement of gases 209 in FIG. 10).

Next, the semiconductor layer 107 a including an amorphous semiconductorand the crystal region 107 b are formed over an entire surface of thegate insulating layer 105. Here, for example, a semiconductor layerincluding the semiconductor layer 107 a including an amorphoussemiconductor and the crystal region 107 b with a total thickness ofabout 50 nm is formed in such a manner that the source gases areintroduced and stabilized, where the flow rate of SiH₄ is 10 sccm andthe flow rate of H₂ is 1500 sccm, and plasma discharge with an output of50 W is performed, where the pressure in the treatment chamber is 280 Paand the temperature of the substrate is 280° C. After that, only thesupply of SiH₄ is stopped, and after several seconds, the plasmadischarge is stopped (formation of a-Si 223 and formation of crystalregion 225 in FIG. 10). After that, these gases are exhausted and gasesfor depositing the microcrystalline semiconductor layer 109 to which animpurity imparting one conductivity type is added are introduced(replacement of gases 217 in FIG. 10).

In the above example, with regard to the source gases for forming thesemiconductor layer 107 a including an amorphous semiconductor and thecrystal region 107 b, the flow rate of H₂ is 150 times that of SiH₄;therefore, the silicon layer is deposited gradually.

Since at least the uppermost layer of the gate insulating layer 105,which is in contact with the semiconductor layer 107 a including anamorphous semiconductor, is formed using a silicon nitride layer in thisembodiment, a large amount of nitrogen exists on the surface of the gateinsulating layer 105. As described above, nitrogen suppresses generationof silicon crystal nuclei. Therefore, as described above, even whendeposition is performed under the condition that the surface of the gateinsulating layer 105 is supplied with nitrogen to form amicrocrystalline silicon layer, the semiconductor layer 107 a includingan amorphous semiconductor is formed. The semiconductor layer 107 aincluding an amorphous semiconductor is formed while the nitrogenconcentration in the semiconductor layer 107 a including an amorphoussemiconductor is reduced. When the nitrogen concentration is a constantvalue or less, crystal nuclei are generated. After that, the crystalnuclei grow, so that the crystal grains are formed and come in contactwith each other and the crystal region 107 b is formed. Note that here,in a generation position of the crystal nucleus, from which the crystalregion 107 b starts to grow, the nitrogen concentration measured bysecondary ion mass spectrometry is from 1×10²⁰ cm⁻³ to 1×10²¹ cm⁻³,preferably from 2×10²⁰ cm⁻³ to 1×10²⁰ cm⁻³, more preferably from 2×10²⁰cm⁻³ to 7×10²⁰ cm⁻³.

Note that, as an impurity element suppressing generation of a crystalnucleus, an impurity element which does not generate a carrier trap insilicon (for example, nitrogen) is selected. On the other hand, theconcentration of an impurity element which reduces the coordinationnumber of silicon and generates a dangling bond (for example, oxygen) isreduced. Accordingly, an oxygen concentration is preferably reducedwithout reduction of the nitrogen concentration. In specific, the oxygenconcentration measured by secondary ion mass spectrometry is preferablyset to 5×10¹⁸ cm⁻³ or less.

As for the profile of SIMS (secondary ion mass spectrometry) of nitrogenin the gate insulating layer, the layer including an amorphoussemiconductor, and the crystal region described in this embodiment, thenitrogen concentration has a peak in the gate insulating layer and thelayer including an amorphous semiconductor and is gradually reduced asthe distance from the bottom of the gate insulating layer in a directionin which the layer including an amorphous semiconductor, the crystalregion, and the source and drain regions are formed increases.

Next, the microcrystalline semiconductor layer 109 to which an impurityimparting one conductivity type is added is formed over an entiresurface of the crystal region 107 b. Here, a microcrystalline siliconlayer containing phosphorus with a thickness of about 30 nm is formed ina manner similar to that of formation of impurity semiconductor layer219 in Embodiment 4. After that, only the supply of SiH₄ is stopped, andafter several seconds, the plasma discharge is stopped (formation ofimpurity semiconductor layer 219 in FIG. 10). After that, these gasesare exhausted (exhaust 221 in FIG. 10).

As described above, by forming at least the gate insulating layer incontact with the layer including an amorphous semiconductor with the useof a silicon nitride layer, the oxygen concentration can be suppressedand can be lower than the nitrogen concentration, whereby the layerincluding an amorphous semiconductor and the crystal region including aninverted conical or pyramidal microcrystalline semiconductor can beformed. Further, since the microcrystalline semiconductor layer to whichan impurity imparting one conductivity type is added is formed over thecrystal region including an inverted conical or pyramidalmicrocrystalline semiconductor, crystal growth of the microcrystallinesemiconductor layer to which an impurity imparting one conductivity typeis added occurs using the crystals of the surface of the crystal regionas seed crystals. Therefore, formation of a low density layer in anearly stage of the deposition can be suppressed.

Embodiment 6

This embodiment will describe a formation method which can be employedinstead of the method for forming the gate insulating layer 105, thesemiconductor layer 107 a including an amorphous semiconductor, and thecrystal region 107 b in Embodiment 5.

Here, a process for forming a silicon nitride layer and a siliconoxynitride layer as the gate insulating layer 105, an amorphous siliconlayer containing nitrogen as the semiconductor layer 107 a including anamorphous semiconductor, an inverted conical or pyramidalmicrocrystalline silicon layer as the crystal region 107 b, and amicrocrystalline silicon layer containing phosphorus as themicrocrystalline semiconductor layer 109 to which an impurity impartingone conductivity type is added will be described with reference to atime chart shown in FIG. 11.

First, the substrate 101 over which the gate electrode layer 103 isformed is heated in a treatment chamber of the CVD apparatus. Then, inorder to form a silicon nitride layer as the gate insulating layer 105,source gases used for depositing the silicon nitride layer areintroduced into the treatment chamber (pretreatment 201 in FIG. 11).Here, a silicon nitride layer with a thickness of about 110 nm is formedin a manner similar to that of formation of SiN 203 described inEmbodiment 4. After that only the supply of SiH₄ is stopped, and afterseveral seconds, the plasma discharge is stopped (formation of SiN 203in FIG. 1).

Next, the source gases used for depositing the silicon nitride layer areexhausted and source gases used for depositing the silicon oxynitridelayer are introduced into the treatment chamber (replacement of gases227 in FIG. 11). Here, for example, a silicon oxynitride layer with athickness of about 110 nm is formed in such a manner that the sourcegases are introduced and stabilized, where the flow rate of SiH₄ is 30sccm and the flow rate of N₂O is 1200 sccm, and plasma discharge with anoutput of 50 W is performed, where the pressure in the treatment chamberis 40 Pa and the temperature of the substrate is 280° C. After that in amanner similar to that of formation of the silicon nitride layer, onlythe supply of SiH₄ is stopped, and after several seconds, the plasmadischarge is stopped (formation of SiON 229 in FIG. 11).

Through the above steps, the gate insulating layer 105 can be formed.After the gate insulating layer 105 is formed, the substrate 101 iscarried out of the treatment chamber (unload 231 in FIG. 11).

After the substrate 101 is carried out of the treatment chamber, forexample, an NF₃ gas is introduced into the treatment chamber and theinside of the treatment chamber is cleaned (cleaning treatment 233 inFIG. 11). After that, treatment for forming an amorphous silicon layeras a protective layer in the treatment chamber is performed (precoatingtreatment 235 in FIG. 11). Here, an amorphous silicon layer is formed ina manner similar to that of precoating treatment 207 in Embodiment 4.Only the supply of SiH₄ is stopped, and after several seconds, theplasma discharge is stopped. After that, these gases are exhausted.After that, the substrate 101 is carried into the treatment chamber(load 237 in FIG. 11).

Next, nitrogen is adsorbed onto the surface of the gate insulating layer105. Here, by exposing the surface of the gate insulating layer 105 toan ammonia gas, nitrogen is supplied (flush treatment 239 in FIG. 11).Further, hydrogen may be contained in the ammonia gas. Here, forexample, preferably, the pressure in the treatment chamber is about 20to 30 Pa, the substrate temperature is 280° C., and the treatment timeis 60 seconds. Note that in the treatment of this step, the substrate101 is only exposed to an ammonia gas; however, plasma treatment mayalso be performed. After that, these gases are exhausted.

Next, the semiconductor layer 107 a including an amorphous semiconductoris formed over an entire surface of the gate insulating layer 105 ontowhich nitrogen is adsorbed. First, source gases for depositing thesemiconductor layer 107 a including an amorphous semiconductor and thecrystal region 107 b are introduced into the treatment chamber(replacement of gases 209 in FIG. 11). Here, for example thesemiconductor layer including the semiconductor layer 107 a including anamorphous semiconductor and the crystal region 107 b with a totalthickness of about 50 nm is formed in such a manner that the sourcegases are introduced and stabilized, where the flow rate of SiH₄ is 10sccm and the flow rate of H₂ is 1500 sccm, and plasma discharge with anoutput of 50 W is performed, where the pressure in the treatment chamberis 280 Pa and the temperature of the substrate is 280° C. After that,only the supply of SiH₄ is stopped, and after several seconds, theplasma discharge is stopped (formation of a-Si 241 and formation ofcrystal region 243 in FIG. 11). After that, these gases are exhaustedand gases for depositing the microcrystalline semiconductor layer 109 towhich an impurity imparting one conductivity type is added areintroduced (replacement of gases 217 in FIG. 11).

In the above example, with regard to the source gases for forming thesemiconductor layer 107 a including an amorphous semiconductor and thecrystal region 107 b, the flow rate of H₂ is 150 times that of SiH₄;therefore, the silicon layer is deposited gradually.

Nitrogen is supplied to the surface of the gate insulating layer 105 inthis embodiment. As described above, nitrogen suppresses generation ofsilicon crystal nuclei. Therefore, silicon crystal nuclei are notgenerated in an early stage of the deposition, and even when depositionis performed under the condition that a microcrystalline silicon layeris formed over the surface of the gate insulating layer 105, thesemiconductor layer 107 a including an amorphous semiconductor isformed. The semiconductor layer 107 a including an amorphoussemiconductor is formed while the nitrogen concentration in thesemiconductor layer 107 a including an amorphous semiconductor isreduced. When the nitrogen concentration is a constant value or less,crystal nuclei are generated. After that, the crystal nuclei grow, sothat the crystal grains are formed and come in contact with each otherand the crystal region 107 b is formed. Note that here, in a generationposition of the crystal nucleus, from which the crystal region 107 bstarts to grow, the nitrogen concentration measured by secondary ionmass spectrometry is from 1×10²⁰ cm⁻³ to 1×10²¹ cm⁻³, preferably from2×10²⁰ cm⁻³ to 1×10²⁰ cm⁻³, more preferably from 2×10²⁰ cm⁻³ to 7×10²⁰cm⁻³.

As for the profile of SIMS (secondary ion mass spectrometry) of nitrogenin the gate insulating layer, the layer including an amorphoussemiconductor, and the crystal region described in this embodiment, thenitrogen concentration has a peak in the gate insulating layer and thelayer including an amorphous semiconductor and is gradually reduced asthe distance from the bottom of the gate insulating layer in a directionin which the layer including an amorphous semiconductor, the crystalregion, and the source and drain regions are formed increases.

Next, the microcrystalline semiconductor layer 109 to which an impurityimparting one conductivity type is added is formed over an entiresurface of the crystal region 107 b. Here, for example, amicrocrystalline silicon layer containing phosphorus with a thickness ofabout 30 nm is formed in a manner similar to that of formation ofimpurity semiconductor layer 219 in Embodiment 4. After that, only thesupply of SiH₄ is stopped, and after several seconds, the plasmadischarge is stopped (formation of impurity semiconductor layer 219 inFIG. 11). After that, these gases are exhausted (exhaust 221 in FIG.11).

As described above, by supplying nitrogen and, additionally, hydrogen tothe surface of the gate insulating layer at least before forming thelayer including an amorphous semiconductor, the oxygen concentration canbe suppressed and can be made to be lower than the nitrogenconcentration, whereby the layer including an amorphous semiconductorand the crystal region including an inverted conical or pyramidalmicrocrystalline semiconductor can be formed. Further, since themicrocrystalline semiconductor layer to which an impurity imparting oneconductivity type is added is formed over the crystal region includingan inverted conical or pyramidal microcrystalline semiconductor, crystalgrowth of the microcrystalline semiconductor layer to which an impurityimparting one conductivity type is added occurs using the crystals ofthe surface of the crystal region as seed crystals. Therefore, formationof a low density layer in an early stage of the deposition can besuppressed.

Embodiment 7

This embodiment will describe a formation method which can be employedinstead of the method for forming the gate insulating layer 105, thesemiconductor layer 107 a including an amorphous semiconductor, and thecrystal region 107 b in Embodiment 5.

Here, a process for forming a silicon nitride layer and a siliconoxynitride layer as the gate insulating layer 105, an amorphous siliconlayer containing nitrogen as the semiconductor layer 107 a including anamorphous semiconductor, an inverted conical or pyramidalmicrocrystalline silicon layer as the crystal region 107 b, and amicrocrystalline silicon layer containing phosphorus as themicrocrystalline semiconductor layer 109 to which an impurity impartingone conductivity type is added will be described with reference to atime chart shown in FIG. 12.

First, the substrate 101 over which the gate electrode layer 103 isformed is heated in a treatment chamber of the CVD apparatus. Then, inorder to form a silicon nitride layer as the gate insulating layer 105,source gases used for depositing the silicon nitride layer areintroduced into the treatment chamber (pretreatment 201 in FIG. 12).Here, a silicon nitride layer with a thickness of about 110 nm is formedin a manner similar to that of formation of SiN 203 described inEmbodiment 4. After that, only the supply of SiH₄ is stopped, and afterseveral seconds, the plasma discharge is stopped (formation of SiN 203in FIG. 12).

Next, the source gases used for depositing the silicon nitride layer areexhausted and source gases for depositing the silicon oxynitride layerare introduced into the treatment chamber (replacement of gases 227 inFIG. 12). Here, a silicon oxynitride layer with a thickness of about 110nm is formed in a manner similar to that of formation of SiON 229 inEmbodiment 6. After that, in a manner similar to that of formation ofthe silicon nitride layer, only the supply of SiH₄ is stopped, and afterseveral seconds, the plasma discharge is stopped (formation of SiON 229in FIG. 12).

Through the above steps, the gate insulating layer 105 can be formed.After the gate insulating layer 105 is formed, the substrate 101 iscarried out of the treatment chamber (unload 231 in FIG. 12).

After the substrate 101 is carried out of the treatment chamber, forexample, an NF₃ gas is introduced into the treatment chamber and theinside of the treatment chamber is cleaned (cleaning treatment 233 inFIG. 12). After that, treatment for forming an amorphous silicon layeras a protective layer in the treatment chamber is performed (precoatingtreatment 235 in FIG. 12). Here, an amorphous silicon layer is formed asa protective layer in a manner similar to that of precoating treatment207 in Embodiment 4. Only the supply of SiH₄ is stopped, and afterseveral seconds, the plasma discharge is stopped. After that these gasesare exhausted. After that, the substrate 101 is carried into thetreatment chamber (load 237 in FIG. 12).

Next, source gases for depositing the semiconductor layer 107 aincluding an amorphous semiconductor are introduced into the treatmentchamber (replacement of gases 209 in FIG. 12). Then, the semiconductorlayer 107 a including an amorphous semiconductor is formed whilenitrogen and hydrogen are supplied to the entire surface of the gateinsulating layer 105. Here, for example, the semiconductor layer 107 aincluding an amorphous semiconductor with a thickness of about 50 nm isformed in such a manner that the source gases are introduced andstabilized, where the flow rate of SiH₄ is 20 sccm, the flow rate of H₂is 1250 sccm, and the flow rate of 100 ppm of NH₃ (diluted withhydrogen) is 250 sccm, and plasma discharge with an output of 50 W isperformed, where the pressure in the treatment chamber is 280 Pa and thetemperature of the substrate is 280° C. (formation of a-Si 242 in FIG.12). Note that instead of NH₃, N₂ may be introduced into the treatmentchamber as shown by a dashed line.

Next, by stopping the introduction of the gas for supplying nitrogen,here, NH₃, the nitrogen concentration in the treatment chamber isreduced, so that generation of crystal nuclei is facilitated, crystalsgrow from the crystal nuclei, and the crystal region 107 b is formed(formation of crystal region 243 in FIG. 12). After that, only thesupply of SiH₄ is stopped, and after several seconds, the plasmadischarge is stopped. After that, these gases are exhausted.

In the above example, with regard to the source gases for forming thesemiconductor layer 107 a including an amorphous semiconductor and thecrystal region 107 b, the flow rate of H₂ is 150 times that of SiH₄;therefore, the silicon layer is deposited gradually.

The layer including an amorphous semiconductor is formed while nitrogenand, additionally, hydrogen are supplied in this embodiment. Asdescribed above, nitrogen suppresses generation of silicon crystalnuclei. Therefore, while nitrogen is supplied, silicon crystal nucleiare not generated even if deposition is performed under the conditionthat a microcrystalline silicon layer is formed. This layer formed underthe condition is the semiconductor layer 107 a including an amorphoussemiconductor illustrated in FIG. 6A. At the time of formation of thesemiconductor layer 107 a including an amorphous semiconductor, thesupply of nitrogen is stopped so that the nitrogen concentration in thesemiconductor layer 107 a including an amorphous semiconductor isreduced. When the nitrogen concentration is a constant value or less,crystal nuclei are generated. After that, the crystal nuclei grow, sothat the crystal grains are formed and come in contact with each otherand the crystal region 107 b is formed. Note that here, in a generationposition of the crystal nucleus, from which the crystal region 107 bstarts to grow, the nitrogen concentration measured by secondary ionmass spectrometry is from 1×10²⁰ cm⁻³ to 1×10²¹ cm⁻³, preferably from2×10²⁰ cm⁻³ to 1×10²⁰ cm⁻³, more preferably from 2×10²⁰ cm⁻³ to 7×10²⁰cm⁻³.

As for the profile of SIMS of nitrogen in the gate insulating layer, thelayer including an amorphous semiconductor, and the crystal regiondescribed in this embodiment the nitrogen concentration is substantiallyeven in the gate insulating layer and the layer including an amorphoussemiconductor and is gradually reduced as the distance from theinterface between the layer including an amorphous semiconductor and thecrystal region in a direction in which the source and drain regions areformed increases.

Next, the microcrystalline semiconductor layer 109 to which an impurityimparting one conductivity type is added is formed over an entiresurface of the crystal region 107 b. Here, for example, amicrocrystalline silicon layer containing phosphorus with a thickness ofabout 30 nm is formed in a manner similar to that of formation ofimpurity semiconductor layer 219 in Embodiment 4. After that, only thesupply of SiH₄ is stopped, and after several seconds, the plasmadischarge is stopped (formation of impurity semiconductor layer 219 inFIG. 12). After that, these gases are exhausted (exhaust 221 in FIG.12).

As described above, by supplying nitrogen and, additionally, hydrogen atthe time of forming the layer including an amorphous semiconductor, theoxygen concentration can be suppressed and can be made to be lower thanthe nitrogen concentration, whereby the layer including an amorphoussemiconductor and the crystal region including an inverted conical orpyramidal microcrystalline semiconductor can be formed. Further, sincethe microcrystalline semiconductor layer to which an impurity impartingone conductivity type is added is formed over the crystal regionincluding an inverted conical or pyramidal microcrystallinesemiconductor, crystal growth of the microcrystalline semiconductorlayer to which an impurity imparting one conductivity type is addedoccurs using the crystals of the surface of the crystal region as seedcrystals. Therefore, formation of a low density layer in an early stageof the deposition can be suppressed.

Embodiment 8

This embodiment will describe a manufacturing process of the thin filmtransistor in FIG. 1B described in Embodiment 1 with reference to FIGS.13A and 13B.

In a manner similar to that of Embodiment 4, the gate electrode layer103 is formed over the substrate 101. Then, the gate insulating layer105 is formed so as to cover the gate electrode layer 103. Then, amicrocrystalline semiconductor layer 139 is formed over the gateinsulating layer 105. Then, the semiconductor layer 107, themicrocrystalline semiconductor layer 109 to which an impurity impartingone conductivity type is added, and the conductive layer 111 are formedover the microcrystalline semiconductor layer 139. After that, theresist mask 113 having regions with different thicknesses is formed overthe conductive layer 111 (see FIG. 13A).

The microcrystalline semiconductor layer 139 can be formed in a similarmanner to the crystal region 107 b described in Embodiment 4.

Here, a process for forming a silicon nitride layer and a siliconoxynitride layer as the gate insulating layer 105, a microcrystallinesilicon layer as the microcrystalline semiconductor layer 139, anamorphous silicon layer as the semiconductor layer 107 a including anamorphous semiconductor, an inverted conical or pyramidalmicrocrystalline silicon layer as the crystal region 107 b, and amicrocrystalline silicon layer containing phosphorus as themicrocrystalline semiconductor layer 109 to which an impurity impartingone conductivity type is added will be described with reference to atime chart shown in FIG. 14. Note that in the case where themicrocrystalline semiconductor layer 139 is in contact with the gateinsulating layer 105, an uppermost surface of the gate insulating layer105 is preferably a silicon oxide layer or a silicon oxynitride layer.Therefore, a silicon nitride layer and a silicon oxynitride layer arestacked as the gate insulating layer 105 here.

First, the substrate 101 over which the gate electrode layer 103 isformed is heated in a treatment chamber of the CVD apparatus. Then, inorder to form a silicon nitride layer as the gate insulating layer 105,source gases for depositing the silicon nitride layer are introducedinto the treatment chamber (pretreatment 201 in FIG. 14). Here, asilicon nitride layer with a thickness of about 110 nm is formed in amanner similar to that of formation of SiN 203 described in Embodiment4. After that, only the supply of SiH₄ is stopped, and after severalseconds, the plasma discharge is stopped (formation of SiN 203 in FIG.14).

Next, the source gases used for depositing the silicon nitride layer areexhausted and source gases for depositing the silicon oxynitride layerare introduced into the treatment chamber (replacement of gases 205 inFIG. 14). Here, for example, a silicon oxynitride layer with a thicknessof about 110 nm is formed in a manner similar to that of formation ofSiON 229 in Embodiment 6. After that, in a manner similar to that offormation of the silicon nitride layer, only the supply of SiH₄ isstopped, and after several seconds, the plasma discharge is stopped(formation of SiON 229 in FIG. 14).

Through the above steps, the gate insulating layer 105 can be formed.After the gate insulating layer 105 is formed, the substrate 101 iscarried out of the treatment chamber (unload 231 in FIG. 14).

After the substrate 101 is carried out of the treatment chamber, forexample, an NF₃ gas is introduced into the treatment chamber and theinside of the treatment chamber is cleaned (cleaning treatment 233 inFIG. 14). After that, treatment for forming an amorphous silicon layeras a protective layer in the treatment chamber is performed (precoatingtreatment 235 in FIG. 14). Here, an amorphous silicon layer is formed asa protective layer in a manner similar to that of precoating treatment207 in Embodiment 4. Only the supply of SiH₄ is stopped, and afterseveral seconds, the plasma discharge is stopped. After that, thesegases are exhausted. After that, the substrate 101 is carried into thetreatment chamber (load 237 in FIG. 14).

Next, the microcrystalline silicon layer is formed as themicrocrystalline semiconductor layer 139 over an entire surface of thegate insulating layer 105. First, source gases for forming themicrocrystalline silicon layer as the microcrystalline semiconductorlayer 139 are introduced into the treatment chamber. Here, amicrocrystalline silicon layer with a thickness of from 2 nm to 100 nm,preferably from 5 nm to 50 nm is formed in a manner similar to that offormation of μc-Si 245 in Embodiment 4. After that, only the supply ofSiH₄ is stopped, and after several seconds, the plasma discharge isstopped. After that, these gases are exhausted (formation of μc-Si 245in FIG. 14).

After that, replacement of gases 209, and in a manner similar to that ofEmbodiment 4, formation of a layer including an amorphous semiconductor(formation of a-Si 211), replacement of gases 213, formation of acrystal region (formation of crystal region 215), replacement of gases217, formation of a microcrystalline semiconductor layer to which animpurity imparting one conductivity type is added (formation of impuritysemiconductor layer 219), and exhaust 221 are performed. Note that atthe time of formation of the layer including an amorphous semiconductor(formation of a-Si 211), crystal growth is likely to occur using themicrocrystalline semiconductor layer 139 as a seed crystal. Therefore, agas containing nitrogen, such as N₂ or NH₃, is introduced into thetreatment chamber in an early stage of the deposition as shown by adashed line, which facilitates amorphization and thus the layerincluding an amorphous semiconductor is easily formed over themicrocrystalline semiconductor layer 139.

Next, the microcrystalline semiconductor layer 139, the semiconductorlayer 107, the microcrystalline semiconductor layer 109 to which animpurity imparting one conductivity type is added, and the conductivelayer 111 are etched with the use of the resist mask 113. Through thisstep, the microcrystalline semiconductor layer 139, the semiconductorlayer 107, the microcrystalline semiconductor layer 109 to which animpurity imparting one conductivity type is added, and the conductivelayer 111 are separated for each element, so that the microcrystallinesemiconductor layer 131, the semiconductor layer 115, themicrocrystalline semiconductor layer 117 to which an impurity impartingone conductivity type is added, and the conductive layer 119 are formed(see FIG. 13B).

After that, through the steps in FIG. 6C and FIGS. 7A and 7B in a mannersimilar to that of Embodiment 4, a thin film transistor in which an oncurrent and field effect mobility are further increased can bemanufactured as illustrated in FIG. 1B.

Note that although the thin film transistor illustrated in FIG. 1B isused as an example in this embodiment the process can be applied to amethod for manufacturing the thin film transistor illustrated in FIG. 3Bas appropriate.

Embodiment 9

This embodiment will describe a manufacturing process of the thin filmtransistor in FIG. 3A described in Embodiment 1 with reference to FIGS.15A to 15C.

In a manner similar to that of Embodiment 4, the gate electrode layer103 is formed over the substrate 101. Then, the gate insulating layer105 is formed so as to cover the gate electrode layer 103. Then, thesemiconductor layer 107 a including an amorphous semiconductor is formedover the gate insulating layer 105. Then, the surface of thesemiconductor layer 107 a including an amorphous semiconductor isexposed to plasma 135.

Here, the plasma 135 is generated in an atmosphere of halogen such asfluorine or chlorine or an atmosphere of a halide such as hydrogenfluoride, silane fluoride, germanium fluoride, nitrogen trifluoride,chlorine fluoride, bromine fluoride, or iodine fluoride, and the surfaceof the semiconductor layer 107 a including an amorphous semiconductor isexposed to the plasma 135. Alternatively, after the plasma 135 isgenerated in an atmosphere of halogen such as fluorine or chlorine or anatmosphere of a halide such as hydrogen fluoride, silane fluoride,germanium fluoride, nitrogen trifluoride, chlorine fluoride, brominefluoride, or iodine fluoride, and the surface of the semiconductor layer107 a including an amorphous semiconductor is exposed to the plasma 135,plasma may be generated in a hydrogen atmosphere or a rare gasatmosphere, and the surface of the semiconductor layer 107 a includingan amorphous semiconductor may be exposed to the plasma. Note thatplasma may be generated by introducing hydrogen, a rare gas, and thelike at the same time in an atmosphere of halogen and an atmosphere of ahalide (see FIG. 15A).

As a result, the semiconductor layer 137 containing a halogen elementcan be formed over the surface of the semiconductor layer 107 aincluding an amorphous semiconductor. Since the plasma 135 has a largeetching effect, a dangling bond is exposed while an amorphous portion ofthe surface of the semiconductor layer 107 a including an amorphoussemiconductor is etched. As a result, a low density layer is not formedin an early stage of the deposition of the crystal region 107 b to beformed later and thus the crystal region 107 b with excellentcrystallinity can be formed.

Next, the crystal region 107 b is formed over the semiconductor layer137 containing a halogen element and the microcrystalline semiconductorlayer 109 to which an impurity imparting one conductivity type is addedis formed over the crystal region 107 b (see FIG. 15B). Since as for thecrystal region 107 b, crystal growth occurs using the semiconductorlayer 137 containing a halogen element as a seed crystal, the crystalregion 107 b has excellent crystallinity. Thus, the proportion of thelow density layer at the interface can be reduced. Further, since in thecase of the microcrystalline semiconductor layer to which an impurityimparting one conductivity type is added, similarly, crystal growthoccurs using the crystal region 107 b as a seed crystal, themicrocrystalline semiconductor layer to which an impurity imparting oneconductivity type is added has excellent crystallinity. Thus, theproportion of the low density layer at the interface can be reduced.

Here, a process for forming a silicon nitride layer as the gateinsulating layer 105, an amorphous silicon layer as the semiconductorlayer 107 a including an amorphous semiconductor, a microcrystallinesilicon layer containing fluorine as the semiconductor layer 137containing a halogen element, a microcrystalline silicon layer as thecrystal region 107 b, and a microcrystalline silicon layer containingphosphorus as the microcrystalline semiconductor layer 109 to which animpurity imparting one conductivity type is added will be described withreference to a time chart shown in FIG. 16.

First, the substrate 101 over which the gate electrode layer 103 isformed is heated in a treatment chamber of the CVD apparatus. Then, inorder to form a silicon nitride layer as the gate insulating layer 105,source gases for depositing a silicon nitride layer are introduced intothe treatment chamber (pretreatment 201 in FIG. 16). Here, a siliconnitride layer with a thickness of about 110 nm is formed in a mannersimilar to that of formation of SiN 203 described in Embodiment 4. Afterthat, only the supply of SiH₄ is stopped, and after several seconds, theplasma discharge is stopped (formation of SiN 203 in FIG. 16).

Through the above steps, the gate insulating layer 105 can be formed.After the gate insulating layer 105 is formed, the source gases used fordepositing the silicon nitride layer are exhausted, and the substrate101 is carried out of the treatment chamber (unload 206 in FIG. 16).

Next, a source gas for depositing an amorphous silicon layer as aprotective layer is introduced into the treatment chamber and treatmentfor forming the amorphous silicon layer in the treatment chamber isperformed (precoating treatment 207 in FIG. 16). By coating the innerwall of treatment chamber with the amorphous silicon layer, it ispossible to prevent an impurity attached to the inner wall of thetreatment chamber, an element included in the inner wall of thetreatment chamber, or the silicon nitride layer formed as the gateinsulating layer from being mixed into a layer including an amorphoussemiconductor to be formed later. After that, the substrate 101 iscarried into the treatment chamber, and source gases for depositing theamorphous silicon layer as the semiconductor layer 107 a including anamorphous semiconductor are introduced into the treatment chamber (load208 in FIG. 16).

Next, the amorphous silicon layer is formed as the semiconductor layer107 a including an amorphous semiconductor over an entire surface of thegate insulating layer 105. First, an amorphous silicon layer with athickness of about 50 nm is formed through a process similar to that offormation of a-Si 211 in Embodiment 4. After that, only the supply ofSiH₄ is stopped, and after several seconds, the plasma discharge isstopped (formation of a-Si 211 in FIG. 16).

Next, after silane fluoride is introduced into the treatment chamber,plasma is generated, and the surface of the semiconductor layer 107 aincluding an amorphous semiconductor is exposed to the silane fluorideplasma. Thus, a microcrystalline silicon layer containing fluorine isformed as the semiconductor layer 137 containing a halogen element (SiF₄treatment 247 in FIG. 16). Note that at that time, hydrogen and/or arare gas may be introduced into the treatment chamber. Since a halogenelement typified by a fluorine radical has high reactivity, an amorphoussemiconductor component in deposition is etched by fluorine radicals.Accordingly, the microcrystalline silicon layer containing fluorine withexcellent crystallinity can be formed. After that silane fluoride isexhausted (replacement of gases 213 in FIG. 16).

Next, a microcrystalline silicon layer is formed as the crystal region107 b over an entire surface of the semiconductor layer 137 containing ahalogen element. First, source gases for depositing the crystal region107 b are introduced into the treatment chamber. Here, for example, amicrocrystalline silicon layer with a thickness of about 50 nm can beformed in a manner similar to that of formation of crystal region 215described in Embodiment 4. After that, only the supply of SiH₄ isstopped, and after several seconds, the plasma discharge is stopped(formation of crystal region 215 in FIG. 16).

After that, replacement of gases 217, formation of a microcrystallinesemiconductor layer to which an impurity imparting one conductivity typeis added (formation of impurity semiconductor layer 219), and exhaust221 are performed.

After that, through the steps in FIGS. 6A to 6C and FIGS. 7A and 7B in amanner similar to that of Embodiment 4, a thin film transistor in whichan on current and field effect mobility are increased can bemanufactured as illustrated in FIG. 3A and FIG. 15C.

The microcrystalline semiconductor layer is formed over the gateinsulating layer 105 and the semiconductor layer 107 a including anamorphous semiconductor is formed over the microcrystallinesemiconductor layer as in Embodiment 8, and the semiconductor layer 137containing a halogen element is formed over the semiconductor layer 107a including an amorphous semiconductor as in this embodiment, so that athin film transistor in which an on current and field effect mobilityare increased can be manufactured as illustrated in FIG. 3B.

Embodiment 10

This embodiment will describe a manufacturing process of the thin filmtransistor in FIG. 3A described in Embodiment 1, which is different fromthe manufacturing process of Embodiment 8, with reference to FIG. 17.

Here, for a method for forming the semiconductor layer 107 a includingan amorphous semiconductor and the crystal region 107 b, any ofEmbodiments 5 to 7 is used. Although Embodiment 5 is used fordescription as a typical example here, Embodiments 6 and 7 can be usedas appropriate.

Here, a process for forming a silicon nitride layer as the gateinsulating layer 105, an amorphous silicon layer containing nitrogen asthe semiconductor layer 107 a including an amorphous semiconductor, amicrocrystalline silicon layer containing fluorine as the semiconductorlayer 137 containing a halogen element, a microcrystalline silicon layeras the crystal region 107 b, and a microcrystalline silicon layercontaining phosphorus as the microcrystalline semiconductor layer 109 towhich an impurity imparting one conductivity type is added will bedescribed with reference to a time chart shown in FIG. 17.

First, the substrate 101 over which the gate electrode layer 103 isformed is heated in a treatment chamber of the CVD apparatus. Then, inorder to form a silicon nitride layer as the gate insulating layer 105,source gases for depositing the silicon nitride layer are introducedinto the treatment chamber (pretreatment 201 in FIG. 17). Here, asilicon nitride layer with a thickness of about 110 nm is formed in amanner similar to that of formation of SiN 203 described in Embodiment4. After that, only the supply of SiH₄ is stopped, and after severalseconds, the plasma discharge is stopped (formation of SiN 203 in FIG.17).

Through the above steps, the gate insulating layer 105 can be formed.After the gate insulating layer 105 is formed, the source gases used fordepositing the silicon nitride layer are exhausted.

Next, the semiconductor layer 107 a including an amorphous semiconductoris formed over an entire surface of the gate insulating layer 105.First, source gases for depositing the semiconductor layer 107 aincluding an amorphous semiconductor are introduced into the treatmentchamber (replacement of gases 209 in FIG. 17). Here, an amorphoussilicon layer containing nitrogen is formed in a manner similar to thatof formation of a-Si 223 in Embodiment 5. At that time, since thenitrogen concentration in the treatment chamber is reduced by increasingfilm thickness, an inverted conical or pyramidal microcrystallinesilicon layer may be formed over the amorphous silicon layer containingnitrogen. After that, only the supply of SiH₄ is stopped, and afterseveral seconds, the plasma discharge is stopped (formation of a-Si 223in FIG. 17). After that, these gases are exhausted.

In the above example, with regard to the source gases for forming thesemiconductor layer 107 a including an amorphous semiconductor, the flowrate of H₂ is 150 times that of SiH₄; therefore, the silicon layer isdeposited gradually.

Next, after silane fluoride is introduced into the treatment chamber,plasma is generated, and the surface of the semiconductor layer 107 aincluding an amorphous semiconductor is exposed to the silane fluorideplasma. Thus, a microcrystalline silicon layer containing fluorine isformed as the semiconductor layer 137 containing a halogen element. Notethat at that time, hydrogen and/or a rare gas may be introduced into thetreatment chamber. Since a halogen element typified by a fluorineradical has high reactivity, an amorphous semiconductor component indeposition is etched by fluorine radicals. Accordingly, themicrocrystalline silicon layer containing fluorine with excellentcrystallinity can be formed. After that, silane fluoride is exhausted(SiF₄ treatment 247 in FIG. 17).

Next, a microcrystalline silicon layer is formed as the crystal region107 b over an entire surface of the semiconductor layer 137 containing ahalogen element. First, source gases for depositing the crystal region107 b are introduced into the treatment chamber (replacement of gases213 in FIG. 17). Here, for example, a microcrystalline silicon layerwith a thickness of about 50 nm can be formed in a manner similar tothat of formation of crystal region 215 described in Embodiment 4. Afterthat, only the supply of SiH₄ is stopped, and after several seconds, theplasma discharge is stopped (formation of crystal region 215 in FIG.17).

After that, replacement of gases 217, formation of a microcrystallinesemiconductor layer to which an impurity imparting one conductivity typeis added (formation of impurity semiconductor layer 219), and exhaust221 are performed.

After that, through the steps in FIGS. 6A to 6C and FIGS. 7A and 7B in amanner similar to that of Embodiment 4, a thin film transistor in whichan on current and field effect mobility are increased can bemanufactured as illustrated in FIG. 3A.

The microcrystalline semiconductor layer is formed over the gateinsulating layer 105 and the semiconductor layer 107 a including anamorphous semiconductor is formed over the microcrystallinesemiconductor layer as in Embodiment 8, and the semiconductor layer 137containing a halogen element is formed over the semiconductor layer 107a including an amorphous semiconductor as in this embodiment, so that athin film transistor in which an on current and field effect mobilityare increased can be manufactured as illustrated in FIG. 3B.

Embodiment 11

This embodiment will describe a manufacturing process of the thin filmtransistor in FIG. 5 described in Embodiment 1 with reference to FIGS.18A to 18C and FIGS. 19A and 19B.

In a manner similar to that of Embodiment 4, the gate electrode layer103 is formed over the substrate 101. Then, the gate insulating layer105, the semiconductor layer 107, and the microcrystalline semiconductorlayer 109 to which an impurity imparting one conductivity type is addedare formed so as to cover the gate electrode layer 103. After that, aresist mask (not shown) is formed over the microcrystallinesemiconductor layer 109 to which an impurity imparting one conductivitytype is added (see FIG. 18A).

Next, the semiconductor layer 107 and the microcrystalline semiconductorlayer 109 to which an impurity imparting one conductivity type is addedare etched with the use of the resist mask. Through this step, thesemiconductor layer 107 and the microcrystalline semiconductor layer 109to which an impurity imparting one conductivity type is added areseparated for each element, so that the semiconductor layer 115 (thesemiconductor layer 115 a including an amorphous semiconductor and thecrystal region 115 b), and the microcrystalline semiconductor layer 117to which an impurity imparting one conductivity type is added are formed(see FIG. 18B).

Next, the conductive layer 111 is formed over the gate insulating layer105, the semiconductor layer 115 (the semiconductor layer 115 aincluding an amorphous semiconductor and the crystal region 115 b), andthe microcrystalline semiconductor layer 117 to which an impurityimparting one conductivity type is added (see FIG. 18C).

Next, a resist mask (not shown) is formed over the conductive layer 111,and the conductive layer 111 is etched with the use of the resist m ask,so that the source electrode layer 133 s and the drain electrode layer133 d are formed. After that, the resist mask is removed.

Next, the microcrystalline semiconductor layer 117 to which an impurityimparting one conductivity type is added is etched by using the sourceelectrode layer 133 s and the drain electrode layer 133 d as masks, sothat the source region 127 s and the drain region 127 d are formed.Further, the crystal region 115 b is etched, so that the crystal regions129 b and 129 c are formed. Further, part of the semiconductor layer 115a including an amorphous semiconductor is etched, so that thesemiconductor layer 129 a including an amorphous semiconductor isformed.

Through the above steps, the thin film transistor illustrated in FIG. 5can be manufactured.

Note that although the resist mask is removed after the source electrodelayer 133 s and the drain electrode layer 133 d are formed in thisembodiment, the microcrystalline semiconductor layer 117 to which animpurity imparting one conductivity type is added, the crystal region115 b, and part of the semiconductor layer 115 a including an amorphoussemiconductor may be etched without removing the resist mask. By theetching, the microcrystalline semiconductor layer 117 to which animpurity imparting one conductivity type is added is etched with the useof the resist mask; thus, an end portion of the source electrode layer133 s and an end portion of the source region 127 s are misaligned andthe source region 127 s is exposed. Accordingly, a thin film transistorin which an end portion of the source electrode layer 133 d and thedrain region 127 d are misaligned and the drain region 127 d is exposedcan be manufactured.

Note that a method for forming a source electrode layer and a drainelectrode layer, which is described in this embodiment, can be appliedto any of Embodiments 5 to 10 as appropriate.

Embodiment 12

This embodiment will describe a structure of a thin film transistor inwhich a threshold voltage can be controlled.

FIG. 20 illustrates an example of a thin film transistor according tothis embodiment. The thin film transistor illustrated in FIG. 20includes, over the substrate 101, the gate electrode layer 103, thesemiconductor layer 129, the gate insulating layer 105 between the gateelectrode layer 103 and the semiconductor layer 129, the source region127 s and the drain region 127 d which are in contact with thesemiconductor layer 129, the source electrode layer 125 s in contactwith the source region 127 s, and the drain electrode layer 125 d incontact with a drain region 127 d. The source region 127 s and the drainregion 127 d are formed using a microcrystalline semiconductor layer towhich an impurity imparting one conductivity type is added. In thesemiconductor layer 129, regions in contact with the source region 127 sand the drain region 127 d are formed of crystal regions 129 b and 129c. Further, the crystal regions 129 b and 129 c in the semiconductorlayer 129 are not formed in a back channel region and separated fromeach other; thus, they make a pair. Further, the semiconductor layer 129includes the semiconductor layer 129 a including an amorphoussemiconductor. Further, a gate insulating layer 141 provided so as tocover at least the back channel portion of the semiconductor layer 129 aincluding an amorphous semiconductor is provided in a region which isnot overlapped with the source electrode layer 125 s and the drainelectrode layer 125 d. A gate electrode layer 143 overlapping the backchannel portion of the semiconductor layer 129 a including an amorphoussemiconductor is provided over the gate insulating layer 141.

The gate insulating layer 141 can be formed to have a single-layerstructure or a layered structure using any of a silicon nitride layer, asilicon oxynitride layer, and a silicon nitride oxide layer in a mannersimilar to that of the gate insulating layer 105. The gate insulatinglayer 141 is formed to a thickness of from 50 nm to 550 nm, preferablyfrom 50 nm to 300 nm in a manner similar to that of the gate insulatinglayer 105.

The gate electrode layer 143 can be formed using a material similar tothat of the gate electrode layer 103 and the source and drain electrodelayers 125 s and 125 d. By providing the gate electrode layer 143 andcontrolling a voltage applied to the gate electrode layer 143, athreshold voltage of the thin film transistor can be controlled.Therefore, with the structure described in this embodiment, formed is athin film transistor in which an on current and field effect mobilityare increased while an off current is reduced, and the threshold voltageis not likely to be shifted.

Further, a potential of the gate electrode layer 143 at the time whenthe thin film transistor described in this embodiment is on ispreferably equal to that of the gate electrode layer 103, and apotential of the gate electrode layer 143 at the time when the thin filmtransistor is off is preferably held at a certain potential. By thusperforming driving, an on current can be increased and an off currentcan be reduced, so that a thin film transistor with excellent switchingcharacteristics can be obtained.

Embodiment 13

In this embodiment, an element substrate and a display device includingthe element substrate to which any of the thin film transistorsdescribed in Embodiments 1 to 12 can be applied will be described below.As a display device, a liquid crystal display device, a light-emittingdisplay device, electronic paper, and the like are given. The thin filmtransistor described in any of the above embodiments can also be usedfor an element substrate of any other display device. Here, a liquidcrystal display device including the thin film transistor described inEmbodiment 1, typically, a vertical alignment (VA) mode liquid crystaldisplay device will be described with reference to FIGS. 24 and 25.

FIG. 24 illustrates a cross-sectional structure of a pixel portion of aliquid crystal display device. A thin film transistor 303 and acapacitor 305 described in this embodiment are formed over a substrate301. Further, a pixel electrode layer 309 is formed over an insulatinglayer 308 formed over the thin film transistor 303. A source or drainelectrode 307 and the pixel electrode layer 309 of the thin filmtransistor 303 are connected to each other in an opening formed in theinsulating layer 308. An alignment film 311 is formed over the pixelelectrode layer 309.

The capacitor 305 includes a capacitor wiring 304 formed at the sametime as a gate electrode layer 302 of the thin film transistor 303, agate insulating layer 306, and the pixel electrode layer 309.

A stack body including components from the substrate 301 to thealignment film 311 is referred to as an element substrate 313.

A counter substrate 321 is provided with a coloring layer 325 and alight-blocking layer 323 for blocking incidence of light into the thinfilm transistor 303. In addition, a planarizing layer 327 is formed overthe light-blocking layer 323 and the coloring layer 325. A counterelectrode layer 329 is formed over the planarizing layer 327, and analignment film 331 is formed over the counter electrode layer 329.

Note that the light-blocking layer 323, the coloring layer 325, and theplanarizing layer 327 over the counter substrate 321 function as a colorfilter. Note that either or both the light-blocking layer 323 and theplanarizing layer 327 are not necessarily formed over the countersubstrate 321.

The coloring layer has a function of preferentially transmitting lightof a predetermined wavelength range, among light of the wavelength rangeof visible light. In general, a coloring layer which preferentiallytransmits light of a wavelength range of red light, a coloring layerwhich preferentially transmits light of a wavelength range of bluelight, and a coloring layer which preferentially transmits light of awavelength range of green light are combined to be used for a colorfilter. However, the combination of the coloring layers is not limitedto the above combination.

The substrate 301 and the counter substrate 321 are fixed by a sealingmaterial (not shown), and a liquid crystal layer 343 fills on an innerside than the substrate 301, the counter substrate 321, and the sealingmaterial. Further, a spacer 341 is provided to keep a distance betweenthe substrate 301 and the counter substrate 321.

The pixel electrode layer 309, the liquid crystal layer 343, and thecounter electrode layer 329 are overlapped with each other so that aliquid crystal element is formed.

FIG. 25 illustrates a liquid crystal display device different from thatin FIG. 24. Here, a coloring layer is formed not on the side of thecounter substrate 321 but on the side of the substrate 301 provided withthe thin film transistor 303.

FIG. 25 illustrates a cross-sectional structure of a pixel portion of aliquid crystal display device. The thin film transistor 303 and thecapacitor 305 described in this embodiment are formed over the substrate301.

Further, a coloring layer 351 is formed over the insulating layer 308formed over the thin film transistor 303. Further, a protective layer353 is formed over the coloring layer 351 in order to prevent animpurity contained in the coloring layer 351 from being mixed into theliquid crystal layer 343. The pixel electrode layer 309 is formed overthe coloring layer 351 and the protective layer 353. As the coloringlayer 351, a layer which preferentially transmits light of apredetermined wavelength range (red light, blue light, or green light)may be formed for each pixel. Further, since the coloring layer 351 alsofunctions as a planarizing layer, uneven alignment of the liquid crystallayer 343 can be suppressed.

The source or drain electrode 307 and the pixel electrode layer 309 ofthe thin film transistor 303 are connected to each other in an openingformed in the insulating layer 308, the coloring layer 351, and theprotective layer 353. The alignment film 311 is formed over the pixelelectrode layer 309.

The capacitor 305 includes the capacitor wiring 304 formed at the sametime as the gate electrode layer 302 of the thin film transistor 303,the gate insulating layer 306, and the pixel electrode layer 309.

A stack body including components from the substrate 301 to thealignment film 311 is referred to as an element substrate 355.

The counter substrate 321 is provided with the light-blocking layer 323for blocking incidence of light into the thin film transistor 303 andthe planarizing layer 327 covering the light-blocking layer 323 and thecounter substrate 321. The counter electrode layer 329 is formed overthe planarizing layer 327, and the alignment film 331 is formed over thecounter electrode layer 329.

The pixel electrode layer 309, the liquid crystal layer 343, and thecounter electrode layer 329 are overlapped with each other so that aliquid crystal element is formed.

Note that although the VA liquid crystal display device is describedhere as a liquid crystal display device, this embodiment is not limitedthereto. In other words, the element substrate which is formed using thethin film transistor described in Embodiment 12 can be used for an FFSliquid crystal display device, an IPS liquid crystal display device, aTN liquid crystal display device, or any other liquid crystal displaydevice.

Since the thin film transistor with a large on current, high fieldeffect mobility, and a small off current is used as a pixel transistorin the liquid crystal display device of this embodiment, image qualityof the liquid crystal display device can be improved. Further, electriccharacteristics of the thin film transistor is not degraded even whenthe thin film transistor is downsized; therefore, by reducing the areaof the thin film transistor, the aperture ratio of the liquid crystaldisplay device can be increased. Alternatively, the area of a pixel canbe reduced, so that resolution of the liquid crystal display device canbe improved.

Further, in the liquid crystal display device illustrated in FIG. 25,the light-blocking layer 323 and the coloring layer 351 are not formedover the same substrate. Therefore, it is not necessary to increase thearea of the light-blocking layer 323 in order to prevent misalignment ofa mask in formation of the coloring layer 351, which can increase theaperture ratio of a pixel.

Embodiment 14

By being provided with a light-emitting element instead of the alignmentfilm 311, the element substrate 313 described in Embodiment 13 can beused for a light-emitting display device or a light-emitting device. Asfor a light-emitting display device or a light-emitting device, alight-emitting element utilizing electroluminescence is typically givenas a light-emitting element. Light-emitting elements utilizingelectroluminescence are roughly classified according to whether alight-emitting material is an organic compound or an inorganic compound.In general, the former is referred to as organic EL elements and thelatter is referred to as inorganic EL elements.

In the light-emitting display device or the light-emitting device ofthis embodiment, a thin film transistor with a large on current, highfield effect mobility, and a small off current is used as a pixeltransistor; therefore, the light-emitting display device or thelight-emitting device can have favorable image quality (for example,high contrast) and low power consumption.

Embodiment 15

A semiconductor device including the thin film transistor according toany of the above embodiments can be applied to a variety of electronicappliances (including an amusement machine). Examples of electronicappliances are a television set (also referred to as a television or atelevision receiver), a monitor of a computer or the like, electronicpaper, a camera such as a digital camera or a digital video camera, adigital photo frame, a mobile phone handset (also referred to as amobile phone or a mobile phone device), a portable game console, aportable information terminal, an audio reproducing device, alarge-sized game machine such as a pachinko machine, and the like. Inparticular, a liquid crystal display device, a light-emitting device, anelectrophoretic display device, or the like to which the thin filmtransistor according to any of the above embodiments is applied asdescribed in Embodiments 13 and 14 can be used for a display portion ofan electronic appliance. Specific examples will be described below.

A semiconductor device including the thin film transistor according toany of the above embodiments can be applied to electronic paper.Electronic paper can be used for electronic appliances of a variety offields as long as they can display data. For example, electronic papercan be applied to an electronic book (e-book), a poster, atransportation advertisement in a vehicle such as a trains displays ofvarious cards such as a credit card, and the like. Examples of theelectronic appliances are illustrated in FIGS. 26A to 26D.

FIG. 26A illustrates an example of an electronic book 2700. For example,the electronic book 2700 includes two housings, a housing 2701 and ahousing 2703. The housing 2701 and the housing 2703 are combined with ahinge 2711 so that the electronic book 2700 can be opened and closedwith the hinge 2711 as an axis. With such a structure, the electronicbook 2700 can be operated like a paper book.

A display portion 2705 and a display portion 2707 are incorporated inthe housing 2701 and the housing 2703, respectively. The display portion2705 and the display portion 2707 may display one image or differentimages. In the case where the display portion 2705 and the displayportion 2707 display different images, for example, a display portion onthe right side (the display portion 2705 in FIG. 26A) can display textand a display portion on the left side (the display portion 2707 in FIG.26A) can display graphics.

FIG. 26A illustrates an example in which the housing 2701 is providedwith an operation portion and the like. For example, the housing 2701 isprovided with a power switch 2721, an operation key 2723, a speaker2725, and the like. With the operation key 2723, pages can be turned.Note that a keyboard, a pointing device, and the like may be provided onthe surface of the housing, on which the display portion is provided.Further, an external connection terminal (an earphone terminal, a USBterminal, a terminal that can be connected to various cables such as anAC adapter and a USB cable, or the like), a recording medium insertionportion, and the like may be provided on the back surface or the sidesurface of the housing. Further, the electronic book 2700 may have afunction of an electronic dictionary.

The electronic book 2700 may transmit and receive data wirelessly. Thestructure may be employed in which a desired book data or the like ispurchased and downloaded from an electronic book server wirelessly.

FIG. 26C illustrates an example of a television set 9600. In thetelevision set 9600, a display portion 9603 is incorporated in a housing9601. The display portion 9603 can display an image. Further, thehousing 9601 is supported by a stand 9605 here. Any of the displaydevices described in Embodiments 13 and 14 can be applied to the displayportion 9603.

The television set 9600 can be operated by an operation switch of thehousing 9601 or a separate remote controller. Channels and volume can becontrolled by an operation key of the remote controller so that an imagedisplayed on the display portion 9603 can be controlled. Further, theremote controller may be provided with a display portion for displayingdata output from the remote controller.

Note that the television set 9600 is provided with a receiver, a modem,and the like. With the receiver, a general television broadcast can bereceived. Further, when the television set 9600 is connected to acommunication network by wired or wireless connection via the modem,one-way (from a transmitter to a receiver) or two-way (between atransmitter and a receiver or between receivers) data communication canbe performed.

FIG. 26B illustrates an example of a digital photo frame 9700. Forexample, in the digital photo frame 9700, a display portion 9703 isincorporated in a housing 9701. The display portion 9703 can displayvarious images. For example, the display portion 9703 can display dataof an image shot by a digital camera or the like to function as a normalphoto frame.

Note that the digital photo frame 9700 is provided with an operationportion, an external connection portion (a USB terminal, a terminal thatcan be connected to various cables such as a USB cable, or the like), arecording medium insertion portion, and the like. Although they may beprovided on the surface on which the display portion is provided, it ispreferable to provide them on the side surface or the back surface forthe design of the digital photo frame 9700. For example, a memorystoring data of an image shot by a digital camera is inserted in therecording medium insertion portion of the digital photo frame, wherebythe image data can be transferred and displayed on the display portion9703.

The digital photo frame 9700 may transmit and receive data wirelessly.The structure may be employed in which desired image data is transferredwirelessly to be displayed.

FIG. 26D illustrates an example of a mobile phone handset 1000. Themobile phone handset 1000 is provided with a display portion 1002incorporated in a housing 1001, operation buttons 1003 and 1007, anexternal connection port 1004, a speaker 1005, a microphone 1006, andthe like. Any of the display devices described in Embodiments 13 and 14can be applied to the display portion 1002.

The display portion 1002 of the mobile phone handset 1000 illustrated inFIG. 26D is a touchscreen. When the display portion 1002 is touched witha finger or the like, contents displayed on the display portion 1002 canbe controlled. Further, operations such as making calls and composingmails can be performed by touching the display portion 1002 with afinger or the like.

There are mainly three screen modes of the display portion 1002. Thefirst mode is a display mode mainly for displaying an image. The secondmode is an input mode mainly for inputting data such as text. The thirdmode is a display-and-input mode in which two modes of the display modeand the input mode are combined.

For example, in the case of making a call or composing a mail, a textinput mode mainly for inputting text is selected for the display portion1002 so that text displayed on a screen can be inputted. In that case,it is preferable to display a keyboard or number buttons on a large areaof the screen of the display portion 1002.

When a detection device including a sensor for detecting inclination,such as a gyroscope or an acceleration sensor, is provided inside themobile phone handset 1000, display of the display portion 1002 can beautomatically switched by determining the direction of the mobile phonehandset 1000 (whether the mobile phone handset 1000 is placedhorizontally or vertically for a landscape mode or a portrait mode).

The screen modes are switched by touching the display portion 1002 oroperating the operation button 1007 of the housing 1001. Alternatively,the screen modes may be switched depending on the kind of the imagedisplayed on the display portion 1002. For example, when a signal of animage displayed on the display portion is the one of moving image data,the screen mode can be switched to the display mode. When the signal isthe one of text data, the screen mode can be switched to the input mode.

Further, in the input mode, when input by touching the display portion1002 is not performed for a certain period while a signal detected bythe optical sensor in the display portion 1002 is detected, the screenmode may be controlled so as to be switched from the input mode to thedisplay mode.

The display portion 1002 may function as an image sensor. For example,an image of the palm print, the fingerprint, or the like is taken by animage sensor when the display portion 1002 is touched with the palm orthe finger, whereby personal authentication can be performed. Further,by providing a backlight or sensing light source emitting anear-infrared light for the display portion, an image of a finger vein,a palm vein, or the like can be taken.

This embodiment can be combined with any of the structures described inthe other embodiments as appropriate.

EXAMPLE 1

This example will describe a change in proportion of a low density layerat the interface between a base layer and a microcrystalline siliconlayer to which phosphorus is added that functions as source and drainregions with reference to FIGS. 22A and 22B.

FIG. 22A shows an image of a cross section of a sample (sample A)obtained by forming a microcrystalline silicon layer to which phosphorusis added over a microcrystalline silicon layer, which is observed by ascanning transmission electron microscope (STEM). FIG. 22B shows animage of a cross section of a sample (sample B) obtained by forming amicrocrystalline silicon layer to which phosphorus is added over anamorphous silicon layer, which is observed by a STEM.

A method for forming the sample A will be described below.

A silicon nitride layer (SiN) with a thickness of 100 nm is formed overa glass substrate (EAGLE2000 manufactured by Corning Incorporated) by aplasma CVD method. The deposition conditions at this time are asfollows: the source gases are introduced and stabilized, where the flowrate of SiH₄ is 40 sccm, the flow rate of H₂ is 500 sccm, the flow rateof N₂ is 550 sccm, and the flow rate of NH₃ is 140 sccm, and plasmadischarge with an RF power frequency of 13.56 MHz and an RE power of 370W is performed, where the pressure in the treatment chamber is 100 Paand the temperature of the substrate is 280° C.

Next, a silicon layer containing nitrogen (μc-Si) with a thickness of 80nm is formed over the silicon nitride layer (SiN). The depositionconditions at this time are as follows: the source gases are introducedand stabilized, where the flow rate of SiH₄ is 10 sccm and the flow rateof H₂ is 1500 sccm, and plasma discharge with an RF power frequency of13.56 MHz and an RF power of 50 W is performed, where the pressure inthe treatment chamber is 280 Pa and the temperature of the substrate is280° C.

Here, since a silicon layer comes to contain nitrogen in the siliconnitride layer (SiN) while being formed, an amorphous silicon layer isformed at a portion of around 0 nm to 5 nm from the bottom of thesilicon layer containing nitrogen (μc-Si); however, crystal nuclei growat a portion of 5 nm to 15 nm from the bottom of the silicon layercontaining nitrogen (μc-Si), and a microcrystalline silicon region whereinverted conical or pyramidal crystal grains are in contact with eachother is formed at a portion of 15 nm to 80 nm from the bottom of thesilicon layer containing nitrogen (μc-Si).

Next, a microcrystalline silicon layer to which phosphorus is added(μc-Si) is formed over the silicon layer containing nitrogen (μc-Si).The deposition conditions at this time are as follows: the source gasesare introduced and stabilized, where the flow rate of SiH₄ is 10 sccm,the flow rate of a mixed gas in which PH₃ is diluted with H₂ to 0.5 vol% is 30 sccm, and the flow rate of hydrogen is 1500 sccm, and plasmadischarge with an RF power frequency of 13.56 MHz and an RF power of 300W is performed, where the pressure in the treatment chamber is 280 Paand the temperature of the substrate is 280° C.

Next, a method for forming the sample B will be described.

Under conditions similar to those of the sample A, a silicon nitridelayer (SiN) with a thickness of 100 nm is formed over a glass substrateby a plasma CVD method.

Next, an amorphous silicon layer (a-Si) with a thickness of 150 nm isformed over the silicon nitride layer (SiN). The deposition conditionsat this time are as follows: the source gases are introduced andstabilized, where the flow rate of SiH₄ is 280 sccm and the flow rate ofH₂ is 300 sccm, and plasma discharge with an RF power frequency of 13.56MHz and an RF power of 370 W is performed, where the pressure in thetreatment chamber is 170 Pa and the temperature of the substrate is 280°C.

Next, under conditions similar to those of the sample A, amicrocrystalline silicon layer to which phosphorus is added (n⁺μc-Si)with a thickness of 50 nm is formed over the amorphous silicon layer(a-Si).

In FIG. 22A, a region A surrounded by a dashed line is a region in whicha low density layer is not formed at the interface between the siliconlayer containing nitrogen (μc-Si) and the microcrystalline silicon layerto which phosphorus is added (n⁺μc-Si). A white region in a region Bsurrounded by a dashed line is a region in which a low density layer isformed at the interface between the silicon layer containing nitrogen(μc-Si) and the microcrystalline silicon layer to which phosphorus isadded (n⁺μc-Si).

In FIG. 22B, a white region in a region C surrounded by a dashed line isa region in which a low density layer is formed at the interface betweenthe amorphous silicon layer (a-Si) and the microcrystalline siliconlayer to which phosphorus is added (n⁺μc-Si).

It can be observed that in the sample of FIG. 22A, a low density layeris reduced as compared to in the sample of FIG. 22B. According to this,it can be understood that by forming a microcrystalline semiconductorlayer to which an impurity imparting one conductivity type is added,here, the microcrystalline silicon layer to which phosphorus is added(n⁺μc-Si) over a crystal region, here, the microcrystalline siliconregion where inverted conical or pyramidal crystal grains are in contactwith each other, the proportion of the low density layer at theinterface between the microcrystalline silicon region where invertedconical or pyramidal crystal grains are in contact with each other andthe microcrystalline silicon layer to which phosphorus is added(n⁺μc-Si) can be reduced.

EXAMPLE 2

This example will describe a change in field effect mobility at the timewhen a channel length is changed in a thin film transistor having thestructure according to any of the above embodiments with reference toFIGS. 18A to 18C, FIGS. 19A and 19B, and FIG. 23.

First, a process for manufacturing a thin film transistor will bedescribed with reference to FIGS. 18A to 18C, and FIGS. 19A and 19B.

The gate electrode layer 103 is formed over the substrate 101.

Here, a glass substrate (EAGLE2000 manufactured by Corning Incorporated)with a thickness of 0.7 mm is used as the substrate 101.

A molybdenum target is sputtered onto the substrate with argon ions witha flow rate of 50 sccm, so that a molybdenum layer with a thickness of150 nm is formed over the substrate. Next, after the molybdenum layer iscoated with a resist exposure is performed using a first photomask.After that, development is performed, so that a resist mask is formed.

Next, the molybdenum layer is etched with the use of the resist mask, sothat the gate electrode layer 103 is formed. Here, the etching isperformed using an ICP etching apparatus under the condition that theICP power is 800 W, the bias power is 100 W, the pressure is 1.5 Pa, andcarbon fluoride with a flow rate of 25 sccm, chlorine with a flow rateof 25 sccm, and oxygen with a flow rate of 10 sccm are used as etchinggases.

After that, the resist mask is removed.

Next, in samples 1 to 3, the gate insulating layer 105, thesemiconductor layer 107, and the microcrystalline semiconductor layer109 to which an impurity imparting one conductivity type is added aresuccessively formed over the gate electrode layer 103 and the substrate101.

Further, in samples 4 to 6, the gate insulating layer 105, thesemiconductor layer 107, and an amorphous semiconductor layer 149 towhich an impurity imparting one conductivity type is added aresuccessively formed over the gate electrode layer 103 and the substrate101.

Here, tinder conditions similar to those of the silicon nitride layer ofExample 1, a silicon nitride layer with a thickness of 300 nm is formedas the gate insulating layer 105. Further, under conditions similar tothose of the silicon layer containing nitrogen (μc-Si) of Example 1, asilicon layer containing nitrogen with a thickness of 80 nm is formed asthe semiconductor layer 107.

In the samples 1 to 3, under conditions similar to those of themicrocrystalline silicon layer to which phosphorus is added (n⁺μc-Si) inExample 1, a microcrystalline silicon layer to which phosphorus is addedwith a thickness of 80 nm is formed as the microcrystallinesemiconductor layer 109 to which an impurity imparting one conductivitytype is added.

In the samples 4 to 6, an amorphous silicon layer to which phosphorus isadded is formed as the amorphous semiconductor layer 149 to which animpurity imparting one conductivity type is added under the conditionthat the RF power frequency is 13.56 MHz, the RF power is 60 W, thedeposition temperature is 280° C., the flow rate of silane is 100 sccm,the flow rate of 0.5% phosphine (diluted with hydrogen) is 170 sccm, andthe pressure is 170 Pa.

Next, after the microcrystalline semiconductor layer 109 to which animpurity imparting one conductivity type is added or the amorphoussemiconductor layer 149 to which an impurity imparting one conductivitytype is added is coated with a resist, exposure is performed using asecond photomask. After that, development is performed, so that a resistmask is formed. Next, the semiconductor layer 107 and themicrocrystalline semiconductor layer 109 to which an impurity impartingone conductivity type is added or the amorphous semiconductor layer 149to which an impurity imparting one conductivity type is added are etchedusing the resist mask, so that the semiconductor layer 115 and themicrocrystalline semiconductor layer 117 to which an impurity impartingone conductivity type is added or an amorphous semiconductor layer 157to which an impurity imparting one conductivity type is added are formed(see FIG. 18B). Here, the etching is performed using an ICP etchingapparatus under the condition that the ICP power is 150 W, the biaspower is 40 W, the pressure is 1.0 Pa, chlorine with a flow rate of 100sccm is used as an etching gas, and etching time is 82 seconds.

Next, as illustrated in FIG. 18C, the conductive layer 111 which coversthe gate insulating layer 105, the semiconductor layer 115, themicrocrystalline semiconductor layer 117 to which an impurity impartingone conductivity type is added or the amorphous semiconductor layer 157to which an impurity imparting one conductivity type is added is formed.Here, a molybdenum target is sputtered with argon ions with a flow rateof 50 sccm, so that a molybdenum layer with a thickness of 300 nm isformed.

Next, after the conductive layer 111 is coated with a resist, exposureis performed using a third photomask. After that, development isperformed, so that a resist mask is formed. The conductive layer 111 iswet-etched using the resist mask, so that the source electrode layer 133s and the drain electrode layer 133 d are formed as illustrated in FIG.19A. Note that in this example, the source electrode layer 133 s and thedrain electrode layer 133 d are parallel in a plan view.

Next, the microcrystalline semiconductor layer 117 to which an impurityimparting one conductivity type is added or the amorphous semiconductorlayer 159 to which an impurity imparting one conductivity type is addedis etched with the use of the resist mask, so that the source region 127s and the drain region 127 d are formed. Note that in that step, thecrystal region 115 b and the surface of the semiconductor layer 115 aincluding an amorphous semiconductor of the semiconductor layer 115 arealso partly etched, so that the crystal regions 129 b and 129 c and thesemiconductor layer 129 a including an amorphous semiconductor areformed (see FIG. 19B). Here, the etching is performed using an ICPetching apparatus under the condition that the ICP power is 150 W, thebias power is 40 W, the pressure is 1.0 Pa, chlorine with a flow rate of100 sccm is used as an etching gas, and etching time is 36 seconds. Thethickness of the semiconductor layer 129 a including an amorphoussemiconductor in this case is 40 nm.

Next, the surfaces of the crystal regions 129 b and 129 c, thesemiconductor layer 129 a including an amorphous semiconductor, thesource region 127 s and the drain region 127 d are irradiated withcarbon fluoride plasma so that an impurity remaining in thesemiconductor layer 129 a including an amorphous semiconductor isremoved. Here, the etching is performed under the condition that thesource power is 1000 W, the pressure is 0.67 Pa, carbon fluoride with aflow rate of 100 sccm is used as an etching gas, and etching time is 30seconds.

Next, the surfaces of the crystal regions 129 h and 129 c, thesemiconductor layer 129 a including an amorphous semiconductor, thesource region 127 s and the drain region 127 d are irradiated with waterplasma. The condition is that plasma is generated in an atmosphere ofwater vapor with a flow rate of 300 sccm, where the power is 1800 W, thepressure is 66.5 Pa, and irradiation with the plasma is performed for180 seconds. After that, the resist is removed.

Next, a silicon nitride layer is formed as a protective insulatinglayer. A silicon nitride layer with a thickness of 300 nm is formed insuch a manner that the source gases are introduced, where the flow rateof SiH₄ is 20 sccm, the flow rate of NH₃ is 220 sccm, the flow rate ofnitrogen is 450 sccm and the flow rate of hydrogen is 450 sccm, andplasma discharge with an output of 300 W is performed, where thepressure in the treatment chamber is 200 Pa and the temperature of thesubstrate is 250° C.

Next, after the protective insulating layer is coated with a resist,exposure is performed using a fourth photomask. After that, developmentis performed, so that a resist mask is formed. The protective insulatinglayer is partly dry-etched using the resist mask, so that the drainelectrode layer 133 d is exposed. Further, the protective insulatinglayer and the gate insulating layer 105 are partly dry-etched, so thatthe gate electrode layer 103 is exposed. Here, by using an ICP etchingapparatus, after plasma is generated under the condition that the ICPpower is 475 W, the bias power is 300 W, the pressure is 5.5 Pa, theflow rate of CHF₃ is 50 sccm, and the flow rate of helium is 100 sccm,etching is performed for 244 seconds with the use of CHF₃ with a flowrate of 7.5 sccm and helium with a flow rate of 142.5 sccm as etchinggases. After that, the resist mask is removed.

Next, a conductive layer is formed over the protective insulating layer.Here, an ITO with a thickness of 50 nm is formed as the conductive layerby a sputtering method.

Next, after the conductive layer is coated with a resist, exposure isperformed using a fifth photomask. After that, development is performed,so that a resist mask is formed. The conductive layer is partlydry-etched with the use of the resist mask, so that a pixel electrode isformed.

Through the above steps, the thin film transistor and the pixelelectrode connected with the thin film transistor are formed.

In the samples 1 and 4, L/W is 3.4 μm/20 μm. In the samples 2 and 5, L/Wis 9.4 μm/20.9 μm. In the samples 3 and 6, L/W is 99.4 μm/100.9 μm.

Further, the samples 1 to 3 (triangular dots in FIG. 23) are each a thinfilm transistor in which source and drain regions are formed using amicrocrystalline silicon layer to which phosphorus is added. The samples4 to 6 (circular dots in FIG. 23) are each a thin film transistor inwhich source and drain regions are formed using an amorphous siliconlayer to which phosphorus is added.

As shown in FIG. 23, even in the case where the samples 1 to 3 each ofwhich is a thin film transistor in which source and drain regions areformed using a microcrystalline silicon layer to which phosphorus isadded has a small channel length and a small channel width, mobility isnot changed so much.

On the other hand, as the samples 4 to 6 each of which is a thin filmtransistor in which source and drain regions are formed using anamorphous silicon layer to which phosphorus is added have smallerchannel lengths and smaller channel widths, field effect mobility isreduced.

That is, it is understood that since the source and drain regions areformed using an amorphous silicon layer to which phosphorus is addedwith high resistivity, resistance between the source region and thesemiconductor layer and resistance between the drain region and thesemiconductor layer are high. Therefore, a short L length increases anadverse affect of resistance in the regions, which reduces field effectmobility.

On the other hand, in the case where an upper portion of thesemiconductor layer (that is, a base layer of source and drain regions)is a crystal region and a microcrystalline semiconductor layer to whichphosphorus is added is formed over the crystal region, a low densitylayer is not formed at the interface between the semiconductor layer andthe source and drain regions, and the source and drain regions areformed using a microcrystalline silicon layer to which phosphorus isadded with low resistivity. Therefore, it is under stood that resistancebetween the source region and the semiconductor layer and resistancebetween the drain region and the semiconductor layer are low. Thus, evenwhen the channel length is reduced, field effect mobility is notchanged.

This application is based on Japanese Patent Application serial no.2008-228765 filed with Japan Patent Office on Sep. 5, 2008, the entirecontents of which are hereby incorporated by reference.

1. A thin film transistor comprising: a gate electrode layer over asubstrate; a gate insulating layer over the gate electrode layer; alayer including an amorphous semiconductor over the gate insulatinglayer; a pair of crystal regions over the layer including the amorphoussemiconductor; and source and drain regions over and in contact with thepair of crystal regions, the source and drain regions including amicrocrystalline semiconductor layer to which an impurity imparting oneconductivity type is added.
 2. The thin film transistor according toclaim 1, further comprising a source electrode layer over the sourceregion, and a drain electrode layer over the drain region.
 3. The thinfilm transistor according to claim 1, wherein each of the pair ofcrystal regions includes columnar crystal grains, inverted conicalgrains, or pyramidal crystal grains.
 4. The thin film transistoraccording to claim 1, wherein the layer including the amorphoussemiconductor is an amorphous silicon layer, an amorphous silicongermanium layer, an amorphous silicon layer containing nitrogen, or anamorphous silicon germanium layer containing nitrogen.
 5. The thin filmtransistor according to claim 1, wherein the layer including theamorphous semiconductor has crystal grains each with a grain size offrom 1 nm to 10 nm.
 6. The thin film transistor according to claim 1,wherein a concentration of nitrogen of the layer including the amorphoussemiconductor is from 1×10²⁰ cm⁻³ to 1×10²¹ cm⁻³.
 7. The thin filmtransistor according to claim 1, wherein a concentration of oxygen ofthe layer including the amorphous semiconductor measured by secondaryion mass spectrometry is 5×10¹⁸ cm⁻³ or less.
 8. A thin film transistorcomprising: a gate electrode layer over a substrate; a gate insulatinglayer over the gate electrode layer; a layer including an amorphoussemiconductor over the gate insulating layer; a pair of crystal regionsover the layer including the amorphous semiconductor; source and drainregions over and in contact with the pair of crystal regions, the sourceand drain regions including a first microcrystalline semiconductor layerto which an impurity imparting one conductivity type is added; and asecond microcrystalline semiconductor layer between the gate insulatinglayer and the layer including the amorphous semiconductor.
 9. The thinfilm transistor according to claim 8, further comprising a sourceelectrode layer over the source region, and a drain electrode layer overthe drain region.
 10. The thin film transistor according to claim 8,wherein each of the pair of crystal regions includes columnar crystalgrains, inverted conical grains, or pyramidal crystal grains.
 11. Thethin film transistor according to claim 8, wherein the layer includingthe amorphous semiconductor is an amorphous silicon layer, an amorphoussilicon germanium layer, an amorphous silicon layer containing nitrogen,or an amorphous silicon germanium layer containing nitrogen.
 12. Thethin film transistor according to claim 8, wherein the layer includingthe amorphous semiconductor has crystal grains each with a grain size offrom 1 nm to 10 nm.
 13. The thin film transistor according to claim 8,wherein a concentration of nitrogen of the layer including the amorphoussemiconductor is from 1×10²⁰ cm³ to 1×10²¹ cm⁻³.
 14. The thin filmtransistor according to claim 8, wherein a concentration of oxygen ofthe layer including the amorphous semiconductor measured by secondaryion mass spectrometry is 5×10¹⁸ cm⁻³ or less.
 15. A thin film transistorcomprising: a gate electrode layer over a substrate; a gate insulatinglayer over the gate electrode layer; a layer including an amorphoussemiconductor over the gate insulating layer; a pair of crystal regionsover the layer including the amorphous semiconductor; source and drainregions over and in contact with the pair of crystal regions, the sourceand drain regions including a first microcrystalline semiconductor layerto which an impurity imparting one conductivity type is added; and asecond microcrystalline semiconductor layer between the layer includingthe amorphous semiconductor and the pair of crystal regions, the secondmicrocrystalline semiconductor layer containing a halogen element. 16.The thin film transistor according to claim 15, further comprising asource electrode layer over the source region, and a drain electrodelayer over the drain region.
 17. The thin film transistor according toclaim 15, wherein each of the pair of crystal regions includes columnarcrystal grains, inverted conical grains, or pyramidal crystal grains.18. The thin film transistor according to claim 15, wherein the layerincluding the amorphous semiconductor is an amorphous silicon layer, anamorphous silicon germanium layer, an amorphous silicon layer containingnitrogen, or an amorphous silicon germanium layer containing nitrogen.19. The thin film transistor according to claim 15, wherein the layerincluding the amorphous semiconductor has crystal grains each with agrain size of from 1 nm to 10 nm.
 20. The thin film transistor accordingto claim 15, wherein a concentration of nitrogen of the layer includingthe amorphous semiconductor is from 1×10²⁰ cm⁻³ to 1×10²¹ cm⁻³.
 21. Thethin film transistor according to claim 15, wherein a concentration ofoxygen of the layer including the amorphous semiconductor measured bysecondary ion mass spectrometry is 5×10¹⁸ cm⁻³ or less.